ModelSim graphic interface
Standards supported
Assumptions
Sections in this document
Command reference
What is an "HDL item"
Text conventions
Where to find our documentation
Download a free PDF reader with Search
Technical support and updates
Introduction
How do projects differ in version 5.5?
Getting started with projects
Step 1 - Create a new project
Step 2 - Add files to the project
Step 3 - Compile the files
Step 4 - Simulate a design
Other project operations
Customizing project settings
Changing compile order
Grouping files
Setting compiler options
Accessing projects from the command line
System initialization
Files accessed during startup
Environment variables accessed during startup
Initialization sequence
Design library contents
Design library types
Working with design libraries
Managing library contents
Assigning a logical name to a design library
Moving a library
Specifying the resource libraries
Predefined libraries
Alternate IEEE libraries supplied
VITAL 2000 library
Rebuilding supplied libraries
Regenerating your design libraries
Verilog resource libraries
Maintaining 32-bit and 64-bit versions in the same library
Importing FPGA libraries
Compiling VHDL designs
Invoking the VHDL compiler
Dependency checking
Range and index checking
Simulating VHDL designs
Invoking the simulator from the Main window
Invoking Code Coverage with Vsim
Using the TextIO package
Syntax for file declaration
Using STD_INPUT and STD_OUTPUT within ModelSim
TextIO implementation issues
Reading and writing hexadecimal numbers
Dangling pointers
The ENDLINE function
The ENDFILE function
Using alternative input/output files
Providing stimulus
Obtaining the VITAL specification and source code
VITAL packages
ModelSim VITAL compliance
VITAL compliance checking
VITAL compliance warnings
Compiling and Simulating with accelerated VITAL packages
Util package
get_resolution()
init_signal_spy()
to_real()
to_time()
Foreign language interface
Compilation
Incremental compilation
Library usage
Verilog-XL compatible compiler options
Verilog-XL `uselib compiler directive
Simulation
Simulation resolution limit
Event order issues
Verilog-XL compatible simulator options
Compiling for faster performance
Compiling with -fast
Compiling mixed designs with -fast
Compiling gate-level designs with -fast
Referencing the optimized design
Enabling design object visibility with the +acc option
Using pre-compiled libraries
Cell Libraries
Delay modes
System Tasks
IEEE Std 1364 system tasks
Verilog-XL compatible system tasks
$init_signal_spy
Compiler Directives
IEEE Std 1364 compiler directives
Verilog-XL compatible compiler directives
Verilog PLI/VPI
Registering PLI applications
Registering VPI applications
Compiling and linking PLI/VPI applications
The PLI callback reason argument
The sizetf callback function
PLI object handles
Third party PLI applications
Support for VHDL objects
IEEE Std 1364 ACC routines
IEEE Std 1364 TF routines
Verilog-XL compatible routines
64-bit support in the PLI
PLI/VPI tracing
Separate compilers, common libraries
Access limitations in mixed-language designs
Mapping data types
VHDL generics
Verilog parameters
VHDL and Verilog ports
Verilog states
VHDL instantiation of Verilog design units
Component declaration
vgencomp component declaration
Verilog instantiation of VHDL design units
WLF files (datasets)
Saving a simulation to a WLF file
Opening datasets
Viewing dataset structure
Managing datasets
Using datasets with ModelSim commands
Restricting the dataset prefix display
Virtual Objects (User-defined buses, and more)
Virtual signals
Virtual functions
Virtual regions
Virtual types
Dataset, WLF file, and virtual commands
Window overview
Common window features
Quick access toolbars
Drag and Drop
Command history
Automatic window updating
Finding names, searching for values, and locating cursors
Sorting HDL items
Multiple window copies
Saving window layout
Context menus
Menu tear off
Customizing menus and buttons
Combining signals into a user-defined bus
Tree window hierarchical view
Main window
Workspace
Transcript
The Main window menu bar
The Main window toolbar
The Main window status bar
Mouse and keyboard shortcuts
Dataflow window
Link to active cursor in Wave window
Dataflow window menu bar
Tracing HDL items with the Dataflow window
Saving the Dataflow window as a Postscript file
List window
HDL items you can view
The List window menu bar
Setting List window display properties
Adding HDL items to the List window
Editing and formatting HDL items in the List window
Examining simulation results with the List window
Finding items by name in the List window
Searching for item values in the List window
Setting time markers in the List window
List window keyboard shortcuts
Saving List window data to a file
Process window
The Process window menu bar
Signals window
The Signals window menu bar
Selecting HDL item types to view
Forcing signal and net values
Adding HDL items to the Wave and List windows or a WLF file
Finding HDL items in the Signals window
Setting signal breakpoints
Defining clock signals
Source window
The Source window menu bar
The Source window toolbar
Setting file-line breakpoints
Editing the source file in the Source window
Checking HDL item values and descriptions
Finding and replacing in the Source window
Setting tab stops in the Source window
Structure window
The Structure window menu bar
Finding items in the Structure window
Variables window
The Variables window menu bar
Wave window
Pathname pane
Values pane
Waveform pane
Cursor panes
HDL items you can view
Adding HDL items in the Wave window
The Wave window menu bar
The Wave window toolbar
Using Dividers
Splitting Wave window panes
Combining items in the Wave window
Editing and formatting HDL items in the Wave window
Setting Wave window display properties
Setting signal breakpoints
Finding items by name or value in the Wave window
Searching for item values in the Wave window
Using time cursors in the Wave window
Finding a cursor
Making cursor measurements
changing the waveform display range
Saving zoom range and scroll position with bookmarks
Wave window mouse and keyboard shortcuts
Printing and saving waveforms
Compiling with the graphic interface
Locating source errors during compilation
Setting default compile options
Simulating with the graphic interface
Design selection tab
VHDL settings tab
Verilog settings tab
Libraries settings tab
SDF settings tab
SDF options
Setting default simulation options
ModelSim tools
The Button Adder
The Macro Helper
The Tcl Debugger
The GUI Expression Builder
Graphic interface commands
Customizing the interface
Introducing Performance Analysis
A Statistical Sampling Profiler
Getting Started
Interpreting the data
Viewing Performance Analyzer Results
Interpreting the Name Field
Interpreting the Under(%) and In(%) Fields
Differences in the Ranked and Hierarchical Views
Ranked/Hierarchical Profile Window Features
The report option
Performance Analyzer preference variables
Performance Analyzer commands
Enabling Code Coverage
The coverage_summary window
Summary information
Misses tab
Exclusions tab
The coverage_summary window menu bar
The coverage_source window
Excluding lines and files
Merging coverage report files
Exclusion filter files
Code Coverage preference variables
Code Coverage commands
Introduction
Two Modes of Comparison
Comparing Hierarchical and Flattened Designs
Graphic Interface to Waveform Comparison
Opening Dataset Comparison
Adding Signals, Regions and/or Clocks
Setting Compare Options
Wave window display
Printing compare differences
List window display
Waveform Comparison preference variables
Waveform Comparison commands
Specifying SDF files for simulation
Instance specification
SDF specification with the GUI
Errors and warnings
VHDL VITAL SDF
SDF to VHDL generic matching
Resolving errors
Verilog SDF
The $sdf_annotate system task
SDF to Verilog construct matching
Optional edge specifications
Optional conditions
Rounded timing values
SDF for Mixed VHDL and Verilog Designs
Interconnect delays
Troubleshooting
Mistaking a component or module name for an instance label
Forgetting to specify the instance
ModelSim VCD commands and VCD tasks
Creating a VCD file
Flow for four-state VCD file
Flow for extended VCD file
Resimulating a design from a VCD file
A VCD file from source to output
VCD simulator commands
VCD output
Capturing port driver data
Supported TSSI states
Strength values
Port identifier code
Example VCD output from vcd dumpports
VHDL SmartModel interface
Creating foreign architectures with sm_entity
Vector ports
Command channel
SmartModel Windows
Memory arrays
Verilog SmartModel interface
Linking the LMTV interface to the simulator
VHDL Hardware Model interface
Creating foreign architectures with hm_entity
Vector ports
Hardware model commands
Tcl features within ModelSim
Tcl References
Tcl commands
Tcl command syntax
if command syntax
set command syntax
Command substitution
Command separator
Multiple-line commands
Evaluation order
Tcl relational expression evaluation
Variable substitution
System commands
List processing
ModelSim Tcl commands
ModelSim Tcl time commands
Conversions
Relations
Arithmetic
Tcl examples
Example 2
Macros (DO files)
Using Parameters with DO files
Command reference table
.main clear
.wave.tree interrupt
.wave.tree zoomfull
.wave.tree zoomin
.wave.tree zoomlast
.wave.tree zoomout
.wave.tree zoomrange
abort
add button
add list
add_menu
add_menucb
add_menuitem
add_separator
add_submenu
add wave
alias
batch_mode
bd
bookmark add wave
bookmark delete wave
bookmark goto wave
bookmark list wave
bp
cd
change
change_menu_cmd
check contention add
check contention config
check contention off
check float add
check float config
check float off
check stable off
check stable on
checkpoint
compare add
compare annotate
compare clock
compare configure
compare continue
compare delete
compare end
compare info
compare list
compare options
compare reload
compare reset
compare run
compare savediffs
compare saverules
compare see
compare start
compare stop
compare update
configure
coverage clear
coverage reload
coverage report
dataset alias
dataset clear
dataset close
dataset info
dataset list
dataset open
dataset rename
delete
describe
disablebp
disable_menu
disable_menuitem
do
down
drivers
dumplog64
echo
edit
enablebp
enable_menu
enable_menuitem
environment
examine
exit
find
force
getactivecursortime
getactivemarkertime
help
history
lecho
left
log
lshift
lsublist
macro_option
modelsim
next
noforce
nolog
notepad
noview
nowhen
onbreak
onElabError
onerror
pause
play
power add
power report
power reset
printenv
profile clear
profile interval
profile off
profile on
profile option
profile report
project
property list
property wave
pwd
quietly
quit
radix
record
report
restart
restore
resume
right
run
search
searchlog
seetime
shift
show
splitio
status
step
stop
tb
toggle add
toggle report
toggle reset
transcribe
transcript
tssi2mti
up
vcd add
vcd checkpoint
vcd comment
vcd dumpports
vcd dumpportsall
vcd dumpportsflush
vcd dumpportslimit
vcd dumpportsoff
vcd dumpportson
vcd file
vcd files
vcd flush
vcd limit
vcd off
vcd on
vcd2wlf
vcom
vdel
vdir
vgencomp
view
virtual count
virtual define
virtual delete
virtual describe
virtual expand
virtual function
virtual hide
virtual log
virtual nohide
virtual nolog
virtual region
virtual save
virtual show
virtual signal
virtual type
vlib
vlog
vmake
vmap
vsim
vsim<info>
vsource
when
where
wlf2log
write format
write list
write preferences
write report
write transcript
write tssi
write wave
Documentation conventions
Command return values
Command shortcuts
Numbering conventions
VHDL numbering conventions
Verilog numbering conventions
File and directory pathnames
HDL item pathnames
Multiple levels in a pathname
Absolute pathnames
Relative pathnames
Environment variables and pathnames
Indexing signals, memories, and nets
Name case sensitivity
Extended identifiers
Naming fields in VHDL signals
Wildcard characters
ModelSim variables
Simulation time units
Comments in argument files
GUI_expression_format
Expression typing
Signal and subelement naming conventions
Concatenation of signals or subelements
VHDL record field support
Grouping and precedence
Searching for binary signal values in the GUI
Expression syntax
Variable settings report
Personal preferences
Returning to the original ModelSim defaults
Environment variables
Creating environment variables in Windows
Referencing environment variables within ModelSim
Removing temp files (VSOUT)
Preference variables located in INI files
[Library] library path variables
[vcom] VHDL compiler control variables
[vlog] Verilog compiler control variables
[vsim] simulator control variables
[lmc] Logic Modeling variables
Setting variables in INI files
Reading variable values from the INI file
Commonly used INI variables
Preference variables located in Tcl files
User-defined variables
More preferences
Variable precedence
Simulator state variables
Referencing simulator state variables
Special considerations for $now
Wave window mouse and keyboard shortcuts
List window keyboard shortcuts
Command shortcuts
Mouse and keyboard shortcuts in Main and Source windows
Right mouse button
Starting the license server daemon
Controlling the license file search
Manual start
Automatic start at boot time
What to do if another application uses FLEXlm
Format of the license file
Feature names
Format of the daemon options file
License administration tools
lmdown
lmremove
lmreread
Administration tools for Windows
How to use checkpoint/restore
The difference between checkpoint/restore and restarting
Using macros with restart and checkpoint/restore
Running command-line and batch-mode simulations
Command-line mode
Batch mode
Source code security and -nodebug
Saving and viewing waveforms in batch mode
Setting up libraries for group use
Maintaining 32-bit and 64-bit modules in the same library
Bus contention checking
Bus float checking
Design stability checking
Toggle checking
Detecting infinite zero-delay loops
Referencing source files with location maps
Using location mapping
Pathname syntax
How location mapping works
Mapping with Tcl variables
Improve performance by locking memory on HP-UX 10.2
Improve performance of large simulations on Sun/Solaris
Performance affected by scheduled events being cancelled
Modeling memory in VHDL
Setting up a List trigger with Expression Builder
New features
Command and variable changes
Documentation changes
GUI changes in version 5.5
Main window changes
Signals window changes
Source window changes
Wave window changes
Coverage_summary window changes
