virtual function

The virtual function command creates a new signal, known only by the GUI (not the kernel), that consists of logical operations on existing signals and simulation time, as described in <expressionString>. It cannot handle bit selects and slices of Verilog registers. Please see "Syntax and conventions" for more details on syntax.

The virtual function will show up in the Wave and Signals windows as an expandible object if it references more than a single scalar signal. The children correspond to the inputs of the virtual function. This allows the virtual function to be "expanded" in the Wave window to see the values of each of the input waveforms, which could be useful when using virtual functions to compare two signal values.

Virtual functions can be used to gate the List window display.

Syntax

virtual function

[-env <path>] [-install <path>] [-implicit] [-delay <time>] {<expressionString>} <name>

Arguments

Arguments for virtual function are the same as those for virtual signal, except for the contents of the expression string.

-env <path>

Specifies a hierarchical context for the signal names in <expressionString> so they don't all have to be full paths. Optional.

-install <path>

Causes the newly-created signal to become a child of the specified region. If install is not specified, the newly-created signal becomes a child of the nearest common ancestor of all objects appearing in <expressionString>. If the expression references more than one WLF file (dataset), the virtual signal will automatically be placed in region
virtuals:/Functions. Optional.

-implicit

Used internally to create virtuals that are automatically saved with the List or Wave format. Optional.

-delay <time>

Specifies a value by which the virtual function will be delayed. Optional. You can use negative values to look forward in time. If units are specified, the <time> option must be enclosed in curly braces. See the examples below for more details.

{<expressionString>}

A text string expression in the MTI GUI expression format. Required. See "GUI_expression_format" for more information.

<name>

The name you define for the virtual signal. Required. Case is ignored unless installed in a Verilog region. Use alpha, numeric, and underscore characters only, unless you are using VHDL extended identifier notation. If using VHDL extended identifier notation, <name> needs to be quoted with double quotes or with curly braces.

Examples

virtual function { not /chip/section1/clk } clk_n

Creates a signal /chip/section1/clk_n which is the inverse of /chip/section1/clk.

virtual function -install /chip { (std_logic_vector) chip.vlog.rega } rega_slv

Creates a std_logic_vector equivalent of a verilog register "rega" and installs it as /chip/rega_slv.

virtual function { /chip/addr[11:0] == 0xfab } addr_eq_fab

Creates a boolean signal /chip/addr_eq_fab that is true when /chip/addr[11:0] is equal to hex "fab", and false otherwise. It is ok to mix VHDL signal path notation with Verilog part-select notation.

virtual function { gate:/chip/siga XOR rtl:/chip/siga) } siga_diff

Creates a signal that is only high during times when signal /chip/siga of the gate-level version of the design does not match /chip/siga of the rtl version of the design. Because there is no common design region for the inputs to the expression, siga_diff is installed in region virtuals:/Functions. The virtual function siga_diff can be added to the wave window, and when expanded will show the two original signals that are being compared.

virtual function -delay {10 ns} {/top/signalA AND /top/signalB} myDelayAandB

Creates a virtual signal consisting of the logical "AND" function of /top/signalA with
/top/signalB, and delays it by 10 ns.

virtual function { | (gate:/chip/outbus XOR rtl:/chip/outbus) } outbus_diff

Creates a one-bit signal "outbus_diff" which is non-zero during times when any bit of a vector signal /chip/outbus of the gate-level version of the design does not match the corresponding bit of the signal in the rtl version of the design.

This expression uses the "OR-reduction" operator, which takes the logical OR of all the bits of the vector argument.

Commands fully compatible with virtual functions

add list	add log /log	add wave
checkpoint and restore	delete	describe ("virtual describe" is a little faster)
down / up	examine	find
restart	left / right	search
searchlog	show

Commands not currently compatible with virtual functions

check contention add	check contention config	check contention off
check float add	check float config	check float off
check stable on	check stable off	drivers
force	noforce	power add
power report	power reset	toggle add
toggle reset	toggle report	vcd add
when

See also

virtual count	virtual define	virtual delete
virtual describe	virtual expand	virtual hide
virtual log	virtual nohide	virtual nolog
virtual region	virtual save	virtual show
virtual signal	virtual type	Virtual Objects (User-defined buses, and more)

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