examine

The examine, or exa command, examines one or more HDL items, and displays current values (or the values at a specified previous time) in the Main window. It optionally can compute the value of an expression of one or more items.

The following items can be examined at any time:

VHDL
signals and process variables

Verilog
nets and register variables

To examine a VHDL variable, the simulator must be paused after a step command, a breakpoint, or you can specify a process label with the name. To display a previous value, specify the desired time using the -time option. To compute an expression, use the -expr option. The -expr and the -time options may be used together.

Virtual signals and functions may also be examined within the GUI (actual signals are examined in the kernel).

Syntax

-time <time>

Specifies the time value between 0 and $now for which to examine the items. If an expression is specified it will be evaluated at that time. Optional.

If the <time> field uses a unit, the value and unit must be placed in curly braces. For example, the following are equivalent for ps resolution:

exa -time {3.6 ns} signal_a exa -time 3600 signal_a

-delta <delta>

Specifies a simulation cycle at the specified time from which to fetch the value. The default is to use the last delta of the time step. Optional.

-env <path>

Specifies a path to look for a signal name. Optional.

-expr <expression>

Specifies an expression to be evaluated. Optional. If the -time argument is present, the expression will be evaluated at the specified time, otherwise it will be evaluated at the current simulation time. See "GUI_expression_format" for the format of the expression. The expression must be placed within curly braces.

-name

Displays signal name(s) along with the value(s). Optional. Default is -value behavior (see below).

The lecho command will return the output of an examine command in prettyprint format. For example,

lecho [examine -name clk prw pstrb]

-<radix>

Specifies the radix for the items that follow in the command. Optional. Valid entries (including unique abbreviations) are:

binary octal decimal (default for integers) or signed hexadecimal unsigned ascii symbolic default

Entries may be truncated to any length, for example, -binary could be expressed as -b or bin, etc. You can change the default radix for the current simulation using the radix command. You can change the default radix permanently by editing the DefaultRadix variable in the modelsim.ini file.

-value

Returns value(s) as a curly-braces separated Tcl list. Default. Use to toggle off a previous use of name.

<name>...

Specifies the name of any HDL item. Required (though not used if the -expr option is used). All item types are allowed, except those of the type file. Multiple names and wildcards are accepted. To examine a VHDL variable you can add a process label to the name. For example (make certain to use two underscore characters):

exa line__36/i

Examples

examine -time {3450 us} -expr {/top/bus and $bit_mask}

In this example the -expr option specifies a signal path and user-defined Tcl variable. The expression will be evaluated at 3450us.

examine -expr {clk'event && (/top/xyz == 16'hffae)}

Because -time is not specified, this expression will be evaluated at the current simulation time. Note the signal attribute and array constant specified in the expression.

Commands like find and examine return their results as a Tcl list (just a blank-separated list of strings). You can do things like:

foreach sig [find ABC*] {echo "Signal $sig is [exa $sig]" ...}

if {[examine -bin signal_12] == "11101111XXXZ"} {...}

examine -hex [find *]




 
 Note: The Tcl variable array, $examine (), can also be used to return values. For example, $examine (/clk). You can also examine an item in the Source window by selecting it with the right mouse button.

examine

Syntax

Arguments

Examples

See also