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drivers
The drivers command displays in the Main window the current value and scheduled future values for all the drivers of a specified VHDL signal or Verilog net. The driver list is expressed relative to the top-most design signal/net connected to the specified signal/net. If the signal/net is a record or array, each subelement is displayed individually. This command reveals the operation of transport and inertial delays and assists in debugging models.
Syntax
driversArguments
<item_name>Specifies the name of the signal or net whose values are to be shown. Required. All signal or net types are valid. Multiple names and wildcards are accepted.
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