Concatenation of signals or subelements

Elements in the concatenation that are arrays are expanded so that each element in the array becomes a top-level element of the concatenation. But for elements in the concatenation that are records, the entire record becomes one top-level element in the result. To specify that the records be broken down so that their subelements become top-level elements in the concatenation, use the "concat_flatten" directive. Currently we do not support leaving full arrays as elements in the result. (Please let us know if you need that option.)

If the elements being concatenated are of incompatible base type, a VHDL-style record will be created. The record object can be expanded in the Signals and Wave windows just like an array of compatible type elements.

Concatenation syntax for VHDL

<signalOrSliceName1> & <signalOrSliceName2> & ... 

Note that the concatenation syntax (below) begins with "&{" rather than just "{". Repetition multipliers are supported, as illustrated in the second line. The repetition element itself may be an arbitrary concatenation subexpression.

Concatenation syntax for Verilog

&{<signalOrSliceName1>, <signalOrSliceName2>, ... }
&{<count>{<signalOrSliceName1>}, <signalOrSliceName2>, ... } 

Concatenation directives

The concatenation directive (as illustrated below) can be used to constrain the resulting array range of a concatenation or influence how compound objects are treated. By default, the concatenation will be created with descending index range from (n-1) downto 0, where n is the number of elements in the array. The "concat_range" directive completely specifies the index range. The "concat_ascending" directive specifies that the index start at zero and increment upwards. The "concat_flatten" directive flattens the signal structure hierarchy. The "concat_sort_wild_ascending" directive gathers signals by name in ascending order (the default is descending).

(concat_range 31:0)<concatenationExpr> # Verilog syntax
(concat_range (31:0))<concatenationExpr> # Also Verilog syntax
(concat_range (31 downto 0))<concatenationExpr> # VHDL syntax
(concat_ascending) <concatenationExpr>
(concat_flatten) <concatenationExpr> 	# no hierarchy
(concat_sort_wild_ascending) <concatenationExpr> 

Examples

&{ "mybusbasename*" } 

Gathers all signals in the current context whose names begin with "mybusbasename", sorts those names in descending order, and creates a bus with index range (n-1) downto 0, where n is the number of matching signals found. (Note that it currently does not derive the index name from the tail of the one-bit signal name.)

(concat_range 13:4)&{ "mybusbasename*" } 

Specifies the index range to be 13 downto 4, with the signals gathered by name in descending order.

(concat_ascending)&{ "mybusbasename*" } 

Specifies an ascending range of 0 to n-1, with the signals gathered by name in descending order.

(concat_ascending)((concat_sort_wild_ascending)&{"mybusbasename*" }) 

Specifies an ascending range of 0 to n-1, with the signals gathered by name in ascending order.

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