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$init_signal_spy

The $init_signal_spy() system task mirrors the value of a VHDL signal or Verilog register/wire (called the spy_object) onto an existing Verilog register or VHDL signal (called the dest_object). This system task allows you to reference VHDL signals at any level of hierarchy from within a Verilog module; or, reference Verilog registers/wires at any level of hierarchy from within a Verilog module when there is an interceding VHDL block.

This system task works only in ModelSim versions 5.5 and newer.

Syntax

$init_signal_spy( spy_object, dest_object, verbose) 

Returns

Nothing

Arguments

Name
Type
Description
spy_object
string

Required. A full hierarchical path (or relative path with reference to the calling block) to a VHDL signal or Verilog register/wire. Use the path separator to which your simulation is set (i.e., "/" or "."). A full hierarchical path must begin with a "/" or ".". The path must be contained within double quotes.

dest_object
string

Required. A full hierarchical path (or relative path with reference to the calling block) to a Verilog register or VHDL signal. Use the path separator to which your simulation is set (i.e., "/" or "."). A full hierarchical path must begin with a "/" or ".". The path must be contained within double quotes.

verbose
integer

Optional. Possible values are 0 or 1. Specifies whether you want a message reported in the Transcript stating that the spy_object's value is mirrored onto the dest_object. Default is 0, no message.

Limitations

Example

module ...
...
reg top_sig1;
...
initial
  begin
    $init_signal_spy("/top/uut/inst1/sig1","/top_sig1", 1);
  end
...
endmodule 

In this example, the value of "/top/uut/inst1/sig1" will be mirrored onto
"/top_sig1".


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