$init_signal_spy
The $init_signal_spy() system task mirrors the value of a VHDL signal or Verilog register/wire (called the spy_object) onto an existing Verilog register or VHDL signal (called the dest_object). This system task allows you to reference VHDL signals at any level of hierarchy from within a Verilog module; or, reference Verilog registers/wires at any level of hierarchy from within a Verilog module when there is an interceding VHDL block.
This system task works only in ModelSim versions 5.5 and newer.
Syntax
$init_signal_spy( spy_object, dest_object, verbose)Returns
Arguments
Limitations
- When mirroring the value of a VHDL signal onto a Verilog register, the VHDL signal must be of type bit, bit_vector, std_logic, or std_logic_vector.
- Mirroring slices or single bits of a vector is not supported. If you do reference a slice or bit of a vector, the function will assume that you are referencing the entire vector.
Example
module ... ... reg top_sig1; ... initial begin $init_signal_spy("/top/uut/inst1/sig1","/top_sig1", 1); end ... endmoduleIn this example, the value of "/top/uut/inst1/sig1" will be mirrored onto
"/top_sig1".
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