Compiler Directives

ModelSim Verilog supports all of the compiler directives defined in the IEEE Std 1364 and some additional Verilog-XL compiler directives for compatibility.

Many of the compiler directives (such as `timescale) take effect at the point they are defined in the source code and stay in effect until the directive is redefined or until it is reset to its default by a `resetall directive. The effect of compiler directives spans source files, so the order of source files on the compilation command line could be significant. For example, if you have a file that defines some common macros for the entire design, then you might need to place it first in the list of files to be compiled.

The `resetall directive affects only the following directives by resetting them back to their default settings (this information is not provided in the IEEE Std 1364):

`celldefine
`default_decay_time
`define_nettype
`delay_mode_distributed
`delay_mode_path
`delay_mode_unit
`delay_mode_zero
`timescale
`unconnected_drive
`uselib 

ModelSim Verilog implicitly defines the following macro:

`define MODEL_TECH 

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