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VHDL Simulation


Chapter contents

Compiling VHDL designs

Creating a design library

Invoking the VHDL compiler

Dependency checking

Range and index checking

Simulating VHDL designs

Invoking the simulator from the Main window

Invoking Code Coverage with Vsim

Using the TextIO package

Syntax for file declaration

Using STD_INPUT and STD_OUTPUT within ModelSim

TextIO implementation issues

Writing strings and aggregates

Reading and writing hexadecimal numbers

Dangling pointers

The ENDLINE function

The ENDFILE function

Using alternative input/output files

Providing stimulus

Obtaining the VITAL specification and source code

VITAL packages

ModelSim VITAL compliance

VITAL compliance checking

VITAL compliance warnings

Compiling and Simulating with accelerated VITAL packages

Util package

get_resolution()

init_signal_spy()

to_real()

to_time()

Foreign language interface

This chapter provides an overview of compilation and simulation for VHDL designs within the ModelSim environment, using the TextIO package with ModelSim; ModelSim's implementation of the VITAL (VHDL Initiative Towards ASIC Libraries) specification for ASIC modeling; and documentation on ModelSim's special built-in utilities package.

The TextIO package is defined within the VHDL Language Reference Manuals, IEEE Std 1076-1987 and IEEE Std 1076-1993; it allows human-readable text input from a declared source within a VHDL file during simulation.

Compiling and simulating with the GUI

Many of the examples in this chapter are shown from the command line. For compiling and simulating within a project or the ModelSim GUI, see:

ModelSim variables

Several variables are available to control simulation, provide simulator state feedback, or modify the appearance of the ModelSim GUI. To take effect, some variables, such as environment variables, must be set prior to simulation. See Appendix A - ModelSim Variables for a complete listing of ModelSim variables.


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