VHDL Simulation
Chapter contents
Invoking the simulator from the Main window
Invoking Code Coverage with Vsim
Using STD_INPUT and STD_OUTPUT within ModelSim
Writing strings and aggregates
Reading and writing hexadecimal numbers
Using alternative input/output files
Obtaining the VITAL specification and source code
Compiling and Simulating with accelerated VITAL packages
This chapter provides an overview of compilation and simulation for VHDL designs within the ModelSim environment, using the TextIO package with ModelSim; ModelSim's implementation of the VITAL (VHDL Initiative Towards ASIC Libraries) specification for ASIC modeling; and documentation on ModelSim's special built-in utilities package.
The TextIO package is defined within the VHDL Language Reference Manuals, IEEE Std 1076-1987 and IEEE Std 1076-1993; it allows human-readable text input from a declared source within a VHDL file during simulation.
Compiling and simulating with the GUI
Many of the examples in this chapter are shown from the command line. For compiling and simulating within a project or the ModelSim GUI, see:
- Getting started with projects
- Compiling with the graphic interface
- Simulating with the graphic interface
ModelSim variables
Several variables are available to control simulation, provide simulator state feedback, or modify the appearance of the ModelSim GUI. To take effect, some variables, such as environment variables, must be set prior to simulation. See Appendix A - ModelSim Variables for a complete listing of ModelSim variables.
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