Simulating VHDL designs

After compiling the design units, you can simulate your designs with vsim. This section discusses simulation from the UNIX or Windows/DOS command line. You can also use a project to simulate (see "Getting started with projects" ) or the Load Design dialog box (see "Simulating with the graphic interface" ).

Note: Simulation normally stops if a failure occurs; however, if a bounds check on a signal fails the simulator will continue running.

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