Simulating with the graphic interface

You can use a project or the Load Design dialog box to simulate a compiled design. For information on simulating in a project, see "Getting started with projects" . To open the Load Design dialog, select the Load Design button (Main window) or Design > Load Design.

Five tabs - Design, VHDL, Verilog, Libraries, and SDF - allow you to select various simulation options.

You can switch between tabs to modify settings, then begin simulation by selecting the Load button. If you select Cancel, all selections remain unchanged and you are returned to the Main window; the Exit button (only active before simulation) closes ModelSim. The Save Settings button allows you to save the preferences on all tabs to a DO (macro) file.

Compile before you simulate

To begin simulation you must have compiled design units located in a design library, see "Creating a design library" .

Note: Many of the dialog box options discussed in this section include parenthetical elements that correspond to vsim command options. For example, Simulator Resolution (-time [<multiplier>]<time_unit>).

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