Design selection tab

Note: The Exit button closes the Load Design dialog box and quits ModelSim.

The Design tab includes these options:

• Library
  Specifies a library to view. Make certain your selection is a valid ModelSim library - the library must be created by ModelSim and it's directory must include a _info file.
• Design Unit
  This hierarchical list allows you to select one top-level entity or configuration to be simulated. All entities, configurations, and modules that exist in the specified library are displayed in the list box. Architectures can be viewed by selecting the "+" box before any name.
• Simulate (<configuration> | <module> | <entity> [(<architecture>)])
  Specifies the design unit(s) to simulate. You can simulate several Verilog top-level modules or a VHDL top-level design unit in one of three ways:

1. Type a design unit name (configuration, module, or entity) into the field, separate additional names with a space. Specify library/design units with the following syntax:

	[<library_name>.]<design_unit> 

2. Click on a name in the Design Unit list below and click the Add button.
3. Leave this field blank and click on a name in the Design Unit list (single unit only).

• Simulator Resolution
  (-time [<multiplier>]<time_unit>)
  The drop-down menu sets the simulator time units (original default is ns).

Simulator time units can be expressed as any of the following:

Simulation time units
1fs, 10fs, or 100fs	femtoseconds
1ps, 10ps, or 100ps	picoseconds
1ns, 10ns, or 100ns	nanoseconds
1us, 10us, or 100us	microseconds
1ms, 10ms, or 100ms	milliseconds
1sec, 10sec, or 100sec	seconds

See also, "Selecting the time resolution" .

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