Syntax for file declaration

The VHDL'87 syntax for a file declaration is:

file identifier : subtype_indication is [ mode ] file_logical_name ; 

where "file_logical_name" must be a string expression.

The VHDL'93 syntax for a file declaration is:

file identifier_list : subtype_indication [ file_open_information ] ; 

You can specify a full or relative path as the file_logical_name; for example (VHDL'87):

file filename : TEXT is in "usr/rick/myfile"; 

Normally if a file is declared within an architecture, process, or package, the file is opened when you start the simulator and is closed when you exit from it. If a file is declared in a subprogram, the file is opened when the subprogram is called and closed when execution RETURNs from the subprogram. Alternatively, the opening of files can be delayed until the first read or write by setting the DelayFileOpen variable in the modelsim.ini file. Also, the number of concurrently open files can be controlled by the ConcurrentFileLimit variable. These variables help you manage a large number of files during simulation. See Appendix A - ModelSim Variables for more details.

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