Grouping files

You can group two or more files in the Project tab. You might do this for organizational purposes or to send the files to the compiler at the same time. For example, you might have one file with a bunch of Verilog define statements and a second file that is a Verilog module. You would want to compile these two files at the same time.

To group files, follow these steps:

1. Right click in an empty area of the Project tab and select Sort by Compile Order.
2. Select the files you want to group.
3. Right click one of the selected files and select Group.

Model Technology Incorporated Voice: (503) 641-1340 Fax: (503)526-5410 www.model.com sales@model.com