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Setting compiler options

The VHDL and Verilog compilers (vcom and vlog, respectively) have numerous options that affect how a design is compiled and subsequently simulated. Outside of a project you can set the defaults for all future simulations using the Options > Compile (Main window) command. Inside of a project you can set these options on individual files or a group of files.

To set the compiler options in a project, select the file(s) in the Project tab, right click on the file names, and select Properties. The resulting dialog varies depending on the number and type of files you have selected. If you select a single VHDL or Verilog file, you'll see the General tab and the VHDL or Verilog tab, respectively. On the General tab, you'll see file properties such as Type, Path, and Size. If you select multiple files, the file properties on the General tab are not listed. Finally, if you select both a VHDL file and a Verilog file, you'll see all three tabs but no file information on the General tab.

The General tab includes these options:

The definitions of the options on the VHDL and Verilog tabs can be found in the section "Setting default compile options" .

When setting options on a group of files, keep in mind the following:


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