Setting default compile options
Select Options > Compile (Main window) to bring up the Compiler Options dialog box shown below. OK accepts the changes made and closes the dialog box. Apply makes the changes with the dialog box open so you can test your settings. Cancel closes the dialog box and makes no changes. The options found on each tab of the dialog box are detailed below. Changes made in the Compiler Options dialog box become the default for all future simulations.
VHDL compiler options tab
- Use 1993 language syntax
Specifies the use of VHDL93 during compilation. The 1987 standard is the default. Same as the -93 switch for the vcom command. Edit the VHDL93 variable in the modelsim.ini file to set a permanent default.
- Don't put debugging info in library
Models compiled with this option do not use any of the ModelSim debugging features. Consequently, your user will not be able to see into the model. This also means that you cannot set breakpoints or single step within this code. Don't compile with this option until you're done debugging. Same as the -nodebug switch for the vcom command. See "Source code security and -nodebug" for more details. Edit the NoDebug variable in the modelsim.ini file to set a permanent default.
- Use explicit declarations only
Used to ignore an error in packages supplied by some other EDA vendors; directs the compiler to resolve ambiguous function overloading in favor of the explicit function definition. Same as the -explicit switch for the vcom command. Edit the Explicit variable in the modelsim.ini file to set a permanent default.
Although it is not intuitively obvious, the = operator is overloaded in the std_logic_1164 package. All enumeration data types in VHDL get an "implicit" definition for the = operator. So while there is no explicit = operator, there is an implicit one. This implicit declaration can be hidden by an explicit declaration of = in the same package (LRM Section 10.3). However, if another version of the = operator is declared in a different package than that containing the enumeration declaration, and both operators become visible through use clauses, neither can be used without explicit naming, for example:
ARITHMETIC."="(left, right)
This option allows the explicit = operator to hide the implicit one.
- Disable loading messages
Disables loading messages in the Main window. Same as the -quiet switch for the vcom command. Edit the Quiet variable in the modelsim.ini file to set a permanent default.
- Show source lines with errors
Causes the compiler to display the relevant lines of code in the transcript. Same as the source switch for the vcom command. Edit the Show_source variable in the modelsim.ini file to set a permanent default.
Flag Warnings on:
- Unbound Component
Flags any component instantiation in the VHDL source code that has no matching entity in a library that is referenced in the source code, either directly or indirectly. Edit the Show_Warning1 variable in the modelsim.ini file to set a permanent default.
- Process without a WAIT statement
Flags any process that does not contain a wait statement or a sensitivity list. Edit the Show_Warning2 variable in the modelsim.ini file to set a permanent default.
- Null Range
Flags any null range, such as 0 down to 4. Edit the Show_Warning3 variable in the modelsim.ini file to set a permanent default.
- No space in time literal (e.g. 5ns)
Flags any time literal that is missing a space between the number and the time unit. Edit the Show_Warning4 variable in the modelsim.ini file to set a permanent default.
- Multiple drivers on unresolved signals
Flags any unresolved signals that have multiple drivers. Edit the Show_Warning5 variable in the modelsim.ini file to set a permanent default.
Check for:
- Synthesis
Turns on limited synthesis-rule compliance checking. Edit the CheckSynthesis variable in the modelsim.ini file to set a permanent default.
- Vital Compliance
Toggle Vital compliance checking. Edit the NoVitalCheck variable in the modelsim.ini file to set a permanent default.
Optimize for:
- StdLogic1164
Causes the compiler to perform special optimizations for speeding up simulation when the multi-value logic package std_logic_1164 is used. Unless you have modified the std_logic_1164 package, this option should always be checked. Edit the Optimize_1164 variable in the modelsim.ini file to set a permanent default.
- Vital
Toggle acceleration of the Vital packages. Edit the NoVital variable in the modelsim.ini file to set a permanent default.
