Enabling design object visibility with the +acc option

Some of the optimizations performed by the -fast option impact design visibility to both the user interface and the PLI routines. Many of the nets, ports, and registers are unavailable by name in user interface commands and in the various graphic interface windows. In addition, many of these objects do not have PLI Access handles, potentially affecting the operation of PLI applications. However, a handle is guaranteed to exist for any object that is an argument to a system task or function.

In the early stages of design, you may choose to compile without the -fast option so as to retain full debug capabilities. Alternatively, you may use one or more +acc options in conjunction with -fast to enable access to specific design objects. However, keep in mind that enabling design object access may reduce simulation performance.

The syntax for the +acc option is as follows:

+acc[=<spec>][+<module>[.]]

<spec> is one or more of the following characters:


<spec>	Meaning
r	Enable access to registers (including memories, integer, time, and real types).
n	Enable access to nets.
b	Enable access to individual bits of vector nets. This is necessary for PLI applications that require handles to individual bits of vector nets. Also, some user interface commands require this access if you need to operate on net bits.
p	Enable access to ports. This disables the module inlining optimization, and should be used for PLI applications that require access to port handles, or for debugging (see below).
c	Enable access to library cells. By default any Verilog module bracketed with a `celldefine / `endcelldefine may be optimized, and debug and PLI access may be limited. This option keeps module cell visibility.

If <spec> is omitted, then access is enabled for all objects.

<module> is a module name, optionally followed by "." to indicate all children of the module. Multiple modules are allowed, each separated by a "+". If no modules are specified, then all modules are affected.

If your design uses PLI applications that look for object handles in the design hierarchy, then it is likely that you will need to use the +acc option. For example, the built-in $dumpvars system task is an internal PLI application that requires handles to nets and registers so that it can call the PLI routine acc_vcl_add to monitor changes and dump the values to a VCD file. This requires that access is enabled for the nets and registers that it operates on. Suppose you want to dump all nets and registers in the entire design, and that you have the following $dumpvars call in your testbench (no arguments to $dumpvars means to dump everything in the entire design):

initial $dumpvars;

Then you need to compile your design as follows to enable net and register access for all modules in the design:

% vlog -fast +acc=rn testbench.v design.v

As another example, suppose you only need to dump nets and registers of a particular instance in the design (the first argument of 1 means to dump just the variables in the instance specified by the second argument):

initial $dumpvars(1, testbench.u1);

Then you need to compile your design as follows (assuming testbench.u1 refers to a module named "design"):

% vlog -fast +acc=rn+design testbench.v design.v

Finally, suppose you need to dump everything in the children instances of testbench.u1 (the first argument of 0 means to also include all children of the instance):

initial $dumpvars(0, testbench.u1);

Then you need to compile your design as follows:

% vlog -fast +acc=rn+design. testbench.v design.v

To gain maximum performance, it may be necessary to enable the minimum required access within the design.