Referencing the optimized design

The compiler automatically assigns a secondary name to distinguish the design-specific optimized code from the unoptimized code that may coexist in the same library. The default secondary name for optimized code is "fast", and the default secondary name for unoptimized code is "verilog". You may specify an alternate name (other than "fast") for optimized code using the -fast=<option>. For example, to assign the secondary name "opt1" to your optimized code, you would enter the following:

% vlog -fast=opt1 cpu_rtl.v 

If you have multiple designs that use common modules compiled into the same library, then you need to assign a different secondary name for each design so that the optimized code for a module used in one design context is not overwritten with the optimized code for the same module used in another context. This is true even if the designs are small variations of each other, such as different testbenches. For example, suppose you have two testbenches that instantiate and test the same design. You might assign different secondary names as follows:

 
% vlog -fast=t1 testbench1.v design.v 
-- Compiling module testbench1 
-- Compiling module design 
 
Top level modules: 
	testbench1 
 
Analyzing design... 
Optimizing 2 modules of which 0 are inlined: 
-- Optimizing module design(t1) 
-- Optimizing module testbench1(t1) 
 
% vlog -fast=t2 testbed2.v design.v 
-- Compiling module testbench2 
-- Compiling module design 
 
Top level modules: 
	testbench2 
 
Analyzing design... 
Optimizing 2 modules of which 0 are inlined: 
-- Optimizing module design(t2) 
-- Optimizing module testbench2(t2) 

All of the modules within design.v compiled for testbench1 are identified by t1 within the library, whereas for testbench2 they are identified by t2. When the simulator loads testbench1, the instantiations from testbench1 reference the t1 versions of the code. Likewise, the instantiations from testbench2 reference the t2 versions. Therefore, you only need to invoke the simulator on the desired top-level module and the correct versions of code for the lower level instances are automatically loaded.

The only time that you need to specify a secondary name to the simulator is when you have multiple secondary names associated with a top-level module. If you omit the secondary name, then, by default, the simulator loads the most recently generated code (optimized or unoptimized) for the top-level module. You may explicitly specify a secondary name to load specific optimized code (specify "verilog" to load the unoptimized code). For example, suppose you have a top-level testbench that works in conjunction with each of several other top-level modules that only contain defparams that configure the design. In this case, you need to compile the entire design for each combination, using a different secondary name for each. For example,

 
% vlog -fast=c1 testbench.v design.v config1.v 
-- Compiling module testbench 
-- Compiling module design 
-- Compiling module config1 
 
Top level modules: 
	testbench 
	config1 
 
Analyzing design... 
Optimizing 3 modules of which 0 are inlined: 
-- Optimizing module design(c1) 
-- Optimizing module testbench(c1) 
-- Optimizing module config1(c1) 
 
% vlog -fast=c2 testbench.v design.v config2.v 
-- Compiling module testbench 
-- Compiling module design 
-- Compiling module config2 
 
Top level modules: 
	testbench 
	config2 
 
Analyzing design... 
Optimizing 3 modules of which 0 are inlined: 
-- Optimizing module design(c2) 
-- Optimizing module testbench(c2) 
-- Optimizing module config2(c2) 

Since the module "testbench" has two secondary names, you must specify which one you want when you invoke the simulator. For example,

% vsim 'testbench(c1)' config1 

Note that it is not necessary to specify the secondary name for config1, because it has only one secondary name. If you omit the secondary name, the simulator defaults to loading the secondary name specified in the most recent compilation of the module.

If you prefer to use the "Load Design" dialog box to select top-level modules, then those modules compiled with -fast can be expanded to view their secondary names. Click on the one you wish to simulate.

To view the library contents, select Design > Browse Libraries to see the modules and their associated secondary names. Also, you can execute the vdir command on a specific module. For example,

VSIM 1> vdir design 
# MODULE design 
#     Optimized Module t1 
#     Optimized Module t2 

Note: In some cases, an optimized module will have "__<n>" appended to its secondary name. This happens when multiple instantiations of a module require different versions of optimized code (for example, when the parameters of each instance are set to different values).

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