Compiling gate-level designs with -fast

Gate-level designs often have large netlists that are slow to compile with -fast. In most cases we recommend the following flow for optimizing gate-level designs:

• Compile the cell library using -fast and the -forcecode argument. The -forcecode argument ensures that code is generated for in-lined modules.
• Compile the device under test and testbench without -fast.
• Create separate work directories for the cell library and the rest of the design.

One case where you wouldn't follow this flow is when the testbench has hierarchical references into the cell library. Optimizing the library alone would result in unresolved references. In such a case, you'll have to compile the library, design, and testbench with fast in one invocation of the compiler. The hierarchical reference cells are then not optimized.

Note too that as of ModelSim version 5.5b, several new switches to vlog can be used to further increase optimizations on gate-level designs. The +nocheck arguments are described in the Command Reference under the vlog command.

You can use the write report command command and the -debugCellOpt argument to vlog command to obtain information about which cells have and have not been optimized. write report produces a text file that lists all modules. Modules with "(cell)" following their names are optimized cells. For example,

Module: top
Architecture: fast 
Module: bottom (cell)
Architecture: fast 

In this case, both top and bottom were compiled with -fast, but top was not optimized and bottom was.

The -debugCellOpt argument is used with -fast when compiling the cell library. Using this argument results in Transcript window output that identifies why certain cells were not optimized.

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