write report

The write report command prints a summary of the design being simulated including a list of all design units (VHDL configurations, entities, and packages and Verilog modules) with the names of their source files. If you have compiled a Verilog design using -fast (see "Compiling for faster performance" ), the report will also identify cells which have been optimized.

Syntax

write report

[[<filename>] [-l | -s] | -tcl]

Arguments

<filename>

Specifies the name of the output file where the data is to be written. Optional. If the <filename> is omitted, the report is written to the Main window.

-l

Generates more detailed information about the design. Default.

-s

Generates a short list of design information. Optional

-tcl

Generates a Tcl list of design unit information. Optional. This argument cannot be used with a filename.

Examples

write report alu.rep

Saves information about the current design in a file named alu.rep.

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