VHDL instantiation of Verilog design units

Once you have generated a component declaration for a Verilog module, you can instantiate the component just like any other VHDL component. In addition, you can reference a Verilog module in the entity aspect of a component configuration - all you need to do is specify a module name instead of an entity name. You can also specify an optional architecture name, but it will be ignored because Verilog modules do not have architectures.

Verilog instantiation criteria

A Verilog design unit may be instantiated from VHDL if it meets the following criteria:

• The design unit is a module (UDPs are not allowed).
• The ports are named ports (Verilog allows unnamed ports).
• The ports are not connected to bidirectional pass switches (it is not possible to handle pass switches in VHDL).

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