Logic Modeling SmartModels

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Chapter contents

VHDL SmartModel interface

Creating foreign architectures with sm_entity

Vector ports

Command channel

SmartModel Windows

Memory arrays

Verilog SmartModel interface

Linking the LMTV interface to the simulator

The Logic Modeling SWIFT-based SmartModel library can be used with ModelSim VHDL and Verilog. The SmartModel library is a collection of behavioral models supplied in binary form with a procedural interface that is accessed by the simulator. This chapter describes how to use the SmartModel library with ModelSim.

Note: The SmartModel library must be obtained from Logic Modeling along with the SmartModel library documentation that describes how to use it. This chapter only describes the specifics of using the library with ModelSim SE.

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