Sections in this document

In addition to this introduction, you will find the following major sections in this document:

2 - Projects and system initialization (2-9)
This chapter provides a definition of a ModelSim "project" and discusses the use of a new file extension for project files.

3 - Design libraries (3-25)
To simulate an HDL design using ModelSim, you need to know how to create, compile, maintain, and delete design libraries as described in this chapter.

4 - VHDL Simulation (4-39)
This chapter is an overview of compilation and simulation for VHDL within the ModelSim environment.

5 - Verilog Simulation (5-57)
This chapter is an overview of compilation and simulation for Verilog within the ModelSim environment.

6 - Mixed VHDL and Verilog Designs (6-111)
ModelSim/Plus single-kernel simulation (SKS) allows you to simulate designs that are written in VHDL and/or Verilog. This chapter outlines data mapping and the criteria established to instantiate design units between HDLs.

7 - WLF files (datasets) and virtuals (7-121)
This chapter describes datasets and virtuals - both methods for viewing and organizing simulation data in ModelSim.

8 - Graphic Interface (8-133)
This chapter describes the graphic interface available while operating ModelSim. ModelSim's graphic interface is designed to provide consistency throughout all operating system environments.

9 - Performance Analyzer (9-265)
This chapter describes how the ModelSim Performance Analyzer is used to easily identify areas in your simulation where performance can be improved.

10 - Code Coverage (10-275)
This chapter describes the Code Coverage feature. Code Coverage gives you graphical and report file feedback on how the source code is being executed.

11 - Waveform Comparison (11-285)
This chapter describes Waveform Comparison, a feature that lets you compare simulations.

12 - Standard Delay Format (SDF) Timing Annotation (12-309)
This chapter discusses ModelSim's implementation of SDF (Standard Delay Format) timing annotation. Included are sections on VITAL SDF and Verilog SDF, plus troubleshooting.

13 - Value Change Dump (VCD) Files (13-323)
This chapter explains Model Technology's Verilog VCD implementation for ModelSim. The VCD usage is extended to include VHDL designs.

14 - Logic Modeling SmartModels (14-335)
This chapter describes the use of the SmartModel Library and SmartModel Windows with ModelSim.

15 - Logic Modeling Hardware Models (15-345)
This chapter describes the use the Logic Modeling Hardware Modeler with ModelSim.

16 - Tcl and macros (16-351)
This chapter provides an overview of Tcl (tool command language) as used with ModelSim.

A - ModelSim Variables (A-679)
This appendix describes environment, system, and preference variables used in ModelSim.

B - ModelSim Shortcuts (B-699)
This appendix describes ModelSim keyboard and mouse shortcuts.

C - Using the FLEXlm License Manager (C-705)
This appendix covers Model Technology's application of FLEXlm for ModelSim licensing.

D - Tips and Techniques (D-713)
This appendix contains an extended collection of ModelSim usage examples taken from our manuals, and tech support solutions.

E - What's new in ModelSim (E-735)
This appendix lists new features and changes in the various versions of ModelSim.

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