Logic Modeling Hardware Models

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Chapter contents

VHDL Hardware Model interface

Creating foreign architectures with hm_entity

Vector ports

Hardware model commands

Logic Modeling hardware models can be used with ModelSim VHDL and Verilog. A hardware model allows simulation of a device using the actual silicon installed as a hardware model in one of Logic Modeling's hardware modeling systems. The hardware modeling system is a network resource with a procedural interface that is accessed by the simulator. This chapter describes how to use Logic Modeling hardware models with ModelSim.

Note: Please refer to the Logic Modeling documentation for details on using the hardware modeler. This chapter only describes the specifics of using hardware models with ModelSim SE.

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