Creating foreign architectures with hm_entity

The ModelSim hm_entity tool automatically creates entities and foreign architectures for hardware models. Its usage is as follows:

Syntax

hm_entity

[-xe] [-xa] [-c] [-93] <shell software filename>

Arguments

-xe

Do not generate entity declarations.

-xa

Do not generate architecture bodies.

-c

Generate component declarations.

-93

Use extended identifiers where needed.

<shell software filename>

Hardware model shell software filename (see Logic Modeling documentation for details on shell software files)

By default, the hm_entity tool writes an entity and foreign architecture to stdout for the hardware model. Optionally, you can include the component declaration (c), exclude the entity (-xe), and exclude the architecture (-xa).

Once you have created the entity and foreign architecture, you must compile it into a library. For example, the following commands compile the entity and foreign architecture for a hardware model named LMTEST:

% hm_entity LMTEST.MDL > lmtest.vhd
% vlib lmc
% vcom -work lmc lmtest.vhd 

To instantiate the hardware model in your VHDL design, you will also need to generate a component declaration. If you have multiple hardware models, you may want to add all of their component declarations to a package so that you can easily reference them in your design. The following command writes the component declaration to stdout for the LMTEST hardware model.

% hm_entity -c -xe -xa LMTEST.MDL 

Paste the resulting component declaration into the appropriate place in your design or into a package.

The following is an example of the entity and foreign architecture created by hm_entity for the CY7C285 hardware model:

library ieee;
use ieee.std_logic_1164.all;

entity cy7c285 is
	generic ( DelayRange : STRING := "Max" );
	port ( A0 : in std_logic;
		A1 : in std_logic;
		A2 : in std_logic;
		A3 : in std_logic;
		A4 : in std_logic;
		A5 : in std_logic;
		A6 : in std_logic;
		A7 : in std_logic;
		A8 : in std_logic;
		A9 : in std_logic;
		A10 : in std_logic;
		A11 : in std_logic;
		A12 : in std_logic;
		A13 : in std_logic;
		A14 : in std_logic;
		A15 : in std_logic;
		CS : in std_logic;
		O0 : out std_logic;
		O1 : out std_logic;
		O2 : out std_logic;
		O3 : out std_logic;
		O4 : out std_logic;
		O5 : out std_logic;
		O6 : out std_logic;
		O7 : out std_logic;
		W : inout std_logic );
end; 
architecture Hardware of cy7c285 is
	attribute FOREIGN : STRING;
	attribute FOREIGN of Hardware : architecture is 
		"hm_init $MODEL_TECH/libhm.sl ; CY7C285.MDL";
begin
end Hardware; 

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