Entity details

• The entity name is the hardware model name (you can manually change this name if you like).
• The port names are the same as the hardware model port names (these names must not be changed). If the hardware model port name is not a valid VHDL identifier, then hm_entity issues an error message. If hm_entity is invoked with the -93 option, then the identifier is converted to an extended identifier, and the resulting entity must also be compiled with the -93 option. Another option is to create a pin-name mapping file. Consult the Logic Modeling documentation for details.
• The port types are std_logic. This data type supports the full range of hardware model logic states.
• The DelayRange generic selects minimum, typical, or maximum delay values. Valid values are "min", "typ", or "max" (the strings are not case-sensitive). The default is "max".

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