Mixed VHDL and Verilog Designs

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Chapter contents

Separate compilers, common libraries

Access limitations in mixed-language designs

Mapping data types

VHDL generics

Verilog parameters

VHDL and Verilog ports

Verilog states

VHDL instantiation of Verilog design units

Verilog instantiation criteria

Component declaration

vgencomp component declaration

Verilog instantiation of VHDL design units

VHDL instantiation criteria

SDF annotation

ModelSim single-kernel simulation (SKS) allows you to simulate designs that are written in VHDL and/or Verilog. This chapter outlines data mapping and the criteria established to instantiate design units between HDLs.

The boundaries between VHDL and Verilog are enforced at the level of a design unit. This means that although a design unit must be either all VHDL or all Verilog, it may instantiate design units from either language. Any instance in the design hierarchy may be a design unit from either HDL without restriction. SKS technology allows the top-level design unit to be either VHDL or Verilog. As you traverse the design hierarchy, instantiations may freely switch back and forth between VHDL and Verilog.

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