Access limitations in mixed-language designs

The Verilog language allows hierarchical access to objects throughout the design. This is not the case with VHDL. You cannot directly read or change a VHDL object (signal, variable, generics, etc.) with a hierarchical reference within a mixed-language design. Furthermore, you cannot directly access a Verilog object farther down the hierarchy if there is an interceding VHDL block.

You have two options for accessing VHDL objects or Verilog objects "obstructed" by an interceding VHDL block: 1) propagate the value through the ports of all design units in the hierarchy; 2) use the Signal Spy function. See "$init_signal_spy" if you are referencing from within a Verilog module or "init_signal_spy()" if you are referencing from within a VHDL module.

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