Mapping data types

Cross-HDL instantiation does not require any extra effort on your part. As ModelSim loads a design it detects cross-HDL instantiations - made possible because a design unit's HDL type can be determined as it is loaded from a library - and the necessary adaptations and data type conversions are performed automatically.

A VHDL instantiation of Verilog may associate VHDL signals and values with Verilog ports and parameters. Likewise, a Verilog instantiation of VHDL may associate Verilog nets and values with VHDL ports and generics. ModelSim automatically maps between the HDL data types as shown below.

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