Verilog Simulation

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Chapter contents

Compilation

Incremental compilation

Library usage

Verilog-XL compatible compiler options

Verilog-XL `uselib compiler directive

Simulation

Invoking the simulator

Simulation resolution limit

Event order issues

Verilog-XL compatible simulator options

Compiling for faster performance

Compiling with -fast

Compiling mixed designs with -fast

Compiling gate-level designs with -fast

Referencing the optimized design

Enabling design object visibility with the +acc option

Using pre-compiled libraries

Cell Libraries

SDF timing annotation

Delay modes

System Tasks

IEEE Std 1364 system tasks

Verilog-XL compatible system tasks

$init_signal_spy

Compiler Directives

IEEE Std 1364 compiler directives

Verilog-XL compatible compiler directives

Verilog PLI/VPI

Registering PLI applications

Registering VPI applications

Compiling and linking PLI/VPI applications

The PLI callback reason argument

The sizetf callback function

PLI object handles

Third party PLI applications

Support for VHDL objects

IEEE Std 1364 ACC routines

IEEE Std 1364 TF routines

Verilog-XL compatible routines

64-bit support in the PLI

PLI/VPI tracing

This chapter describes how to compile and simulate Verilog designs with ModelSim Verilog. ModelSim Verilog implements the Verilog language as defined by the IEEE Std 1364, and it is recommended that you obtain this specification as a reference manual.

In addition to the functionality described in the IEEE Std 1364, ModelSim Verilog includes the following features:

• Standard Delay Format (SDF) annotator compatible with many ASIC and FPGA vendor's Verilog libraries
• Value Change Dump (VCD) file extensions for ASIC vendor test tools
• Dynamic loading of PLI/VPI applications
• Compilation into retargetable, executable code
• Incremental design compilation
• Extensive support for mixing VHDL and Verilog in the same design (including SDF annotation)
• Graphic Interface that is common with ModelSim VHDL
• Extensions to provide compatibility with Verilog-XL

The following IEEE Std 1364 functionality is partially implemented in ModelSim Verilog:

• Verilog Procedural Interface (VPI) (see /<install_dir>/modeltech/docs/technotes/Verilog_VPI.note for details)

Many of the examples in this chapter are shown from the command line. For compiling and simulating within a project or ModelSim's GUI see:

• Getting started with projects
• Compiling with the graphic interface
• Simulating with the graphic interface

ModelSim variables

Several variables are available to control simulation, provide simulator state feedback, or modify the appearance of the ModelSim GUI. To take effect, some variables, such as environment variables, must be set prior to simulation. See Appendix A - ModelSim Variables for a complete listing of ModelSim variables.

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