Incremental compilation

By default, ModelSim Verilog supports incremental compilation of designs, thus saving compilation time when you modify your design. Unlike other Verilog simulators, there is no requirement that you compile the entire design in one invocation of the compiler (although, you may wish to do so to optimize performance; see "Compiling for faster performance" ).

You are not required to compile your design in any particular order because all module and UDP instantiations and external hierarchical references are resolved when the design is loaded by the simulator. Incremental compilation is made possible by deferring these bindings, and as a result some errors cannot be detected during compilation. Commonly, these errors include: modules that were referenced but not compiled, incorrect port connections, and incorrect hierarchical references.

The following example shows how a hierarchical design can be compiled in top-down order:

Contents of top.v:

module top;
	or2(n1, a, b);
	and2(n2, n1, c);
endmodule 

Contents of and2.v:

module and2(y, a, b);
	output y;
	input a, b;
	and(y, a, b);
endmodule 

Contents of or2.v:

module or2(y, a, b); 
	output y;
	input a, b;
	or(y, a, b);
endmodule 

Compile the design in top down order (assumes work library already exists):

% vlog top.v
-- Compiling module top 
Top level modules:
	top
% vlog and2.v
-- Compiling module and2 
Top level modules:
	and2
% vlog or2.v
-- Compiling module or2 
Top level modules:
	or2 

Note that the compiler lists each module as a top level module, although, ultimately, only "top" is a top-level module. If a module is not referenced by another module compiled in the same invocation of the compiler, then it is listed as a top level module. This is just an informative message and can be ignored during incremental compilation. The message is more useful when you compile an entire design in one invocation of the compiler and need to know the top level module names for the simulator. For example,

% vlog top.v and2.v or2.v
-- Compiling module top
-- Compiling module and2
-- Compiling module or2 
Top level modules:
	top 

The most efficient method of incremental compilation is to manually compile only the modules that have changed. This is not always convenient, especially if your source files have compiler directive interdependencies (such as macros). In this case, you may prefer to always compile your entire design in one invocation of the compiler. If you specify the incr option, the compiler will automatically determine which modules have changed and generate code only for those modules. This is not as efficient as manual incremental compilation because the compiler must scan all of the source code to determine which modules must be compiled.

The following is an example of how to compile a design with automatic incremental compilation:

% vlog -incr top.v and2.v or2.v
-- Compiling module top
-- Compiling module and2
-- Compiling module or2 
Top level modules:
	top 

Now, suppose that you modify the functionality of the "or2" module:

% vlog -incr top.v and2.v or2.v
-- Skipping module top
-- Skipping module and2
-- Compiling module or2 
Top level modules:
	top 

The compiler informs you that it skipped the modules "top" and "and2", and compiled "or2".

Automatic incremental compilation is intelligent about when to compile a module. For example, changing a comment in your source code does not result in a recompile; however, changing the compiler command line options results in a recompile of all modules.

Note: Changes to your source code that do not change functionality but that do affect source code line numbers (such as adding a comment line) will cause all affected modules to be recompiled. This happens because debug information must be kept current so that ModelSim can trace back to the correct areas of the source code.

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