Verilog-XL compatible compiler directives

The following compiler directives are provided for compatibility with Verilog-XL.

`default_decay_time <time>

This directive specifies the default decay time to be used in trireg net declarations that do not explicitly declare a decay time. The decay time can be expressed as a real or integer number, or as infinite to specify that the charge never decays.

`delay_mode_distributed

This directive disables path delays in favor of distributed delays. See Delay modes for details.

`delay_mode_path

This directive sets distributed delays to zero in favor of path delays. See Delay modes for details.

`delay_mode_unit

This directive sets path delays to zero and non-zero distributed delays to one time unit. See Delay modes for details.

`delay_mode_zero

This directive sets path delays and distributed delays to zero. See Delay modes for details.

`uselib

This directive is an alternative to the -v, -y, and +libext source library compiler options. See Verilog-XL `uselib compiler directive for details.

The following Verilog-XL compiler directives are silently ignored by ModelSim Verilog. Many of these directives are irrelevant to ModelSim Verilog, but may appear in code being ported from Verilog-XL.

`accelerate
`autoexpand_vectornets
`disable_portfaults
`enable_portfaults
`endprotect
`expand_vectornets
`noaccelerate
`noexpand_vectornets
`noremove_gatenames
`noremove_netnames
`nosuppress_faults
`protect
`remove_gatenames
`remove_netnames
`suppress_faults 

The following Verilog-XL compiler directives produce warning messages in ModelSim Verilog. These are not implemented in ModelSim Verilog, and any code containing these directives may behave differently in ModelSim Verilog than in Verilog-XL.

`default_trireg_strength
`signed
`unsigned 

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