The PLI callback reason argument

The second argument to a PLI callback function is the reason argument. The values of the various reason constants are defined in the veriuser.h include file. See IEEE Std 1364 for a description of the reason constants. The following details relate to ModelSim Verilog, and may not be obvious in the IEEE Std 1364. Specifically, the simulator passes the reason values to the misctf callback functions under the following circumstances:

reason_endofcompile

For the completion of loading the design.

reason_finish

For the execution of the $finish system task or the quit command.

reason_startofsave

For the start of execution of the checkpoint command, but before any of the simulation state has been saved. This allows the PLI application to prepare for the save, but it shouldn't save its data with calls to tf_write_save until it is called with reason_save.

reason_save

For the execution of the checkpoint command. This is when the PLI application must save its state with calls to tf_write_save.

reason_startofrestart

For the start of execution of the restore command, but before any of the simulation state has been restored. This allows the PLI application to prepare for the restore, but it shouldn't restore its state with calls to tf_read_restart until it is called with reason_restart. The reason_startofrestart value is passed only for a restore command, and not in the case that the simulator is invoked with -restore.

reason_restart

For the execution of the restore command. This is when the PLI application must restore its state with calls to tf_read_restart.

reason_reset

For the execution of the restart command. This is when the PLI application should free its memory and reset its state. We recommend that all PLI applications reset their internal state during a restart as the shared library containing the PLI code might not be reloaded. (See the -keeploaded and -keeploadedrestart vsim arguments for related information.)

reason_endofreset

For the completion of the restart command, after the simulation state has been reset but before the design has been reloaded.

reason_interactive

For the execution of the $stop system task or any other time the simulation is interrupted and waiting for user input.

reason_scope

For the execution of the environment command or selecting a scope in the structure window. Also for the call to acc_set_interactive_scope if the callback_flag argument is non-zero.

reason_paramvc

For the change of value on the system task or function argument.

reason_synch

For the end of time step event scheduled by tf_synchronize.

reason_rosynch

For the end of time step event scheduled by tf_rosynchronize.

reason_reactivate

For the simulation event scheduled by tf_setdelay.

reason_paramdrc

Not supported in ModelSim Verilog.

reason_force

Not supported in ModelSim Verilog.

reason_release

Not supported in ModelSim Verilog.

reason_disable

Not supported in ModelSim Verilog.

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