Support for VHDL objects
The PLI ACC routines also provide limited support for VHDL objects in either an all VHDL design or a mixed VHDL/Verilog design. The following table lists the VHDL objects for which handles may be obtained and their type and fulltype constants:
| Type |
Fulltype |
Description |
| accArchitecture |
accArchitecture |
instantiation of an architecture |
| accArchitecture |
accEntityVitalLevel0 |
instantiation of an architecture whose entity is marked with the attribute VITAL_Level0 |
| accArchitecture |
accArchVitalLevel0 |
instantiation of an architecture which is marked with the attribute VITAL_Level0 |
| accArchitecture |
accArchVitalLevel1 |
instantiation of an architecture which is marked with the attribute VITAL_Level1 |
| accArchitecture |
accForeignArch |
instantiation of an architecture which is marked with the attribute FOREIGN and which does not contain any VHDL statements or objects other than ports and generics |
| accArchitecture |
accForeignArchMixed |
instantiation of an architecture which is marked with the attribute FOREIGN and which contains some VHDL statements or objects besides ports and generics |
| accBlock |
accBlock |
block statement |
| accForLoop |
accForLoop |
for loop statement |
| accForeign |
accShadow |
foreign scope created by mti_CreateRegion() |
| accGenerate |
accGenerate |
generate statement |
| accPackage |
accPackage |
package declaration |
| accSignal |
accSignal |
signal declaration |
The type and fulltype constants for VHDL objects are defined in the acc_vhdl.h include file. All of these objects (except signals) are scope objects that define levels of hierarchy in the Structure window. Currently, the PLI ACC interface has no provision for obtaining handles to generics, types, constants, variables, attributes, subprograms, and processes. However, some of these objects can be manipulated through the ModelSim VHDL foreign interface (mti_* routines). See the FLI Reference Manual for more information.
