vcd files

The vcd files command specifies a filename and state mapping for a VCD file created by a vcd add command. The vcd files command is optional. If used, it must be issued before any vcd add commands.

Related Verilog task: $fdumpfile

Syntax

vcd files

<filename> [-nomap] [-map <mapping pairs>] [-direction]

Arguments

<filename>

Specifies the name of a VCD file to create. Required. Multiple files can be opened during a single simulation.

-nomap

Affects only VHDL signals of type std_logic. Optional. It specifies that the values recorded in the VCD file shall use the std_logic enumeration characters of UX01ZWLH. This option results in a non-standard VCD file because VCD values are limited to the four state character set of x01z. By default, the std_logic characters are mapped as follows.

VHDL	VCD	VHDL	VCD
U	x	W	x
X	x	L	0
0	0	H	1
1	1	-	x
Z	z

-map <mapping pairs>

Affects only VHDL signals of type std_logic. Optional. It allows you to override the default mappings. The mapping is specified as a list of character pairs. The first character in a pair must be one of the std_logic characters UX01ZWLH- and the second character is the character you wish to be recorded in the VCD file. For example, to map L and H to z:

vcd files -map "L z H z" 

Note that the quotes in the example above are a Tcl convention for command strings that include spaces.

-direction

Affects only VHDL ports. Optional. It specifies that the variable type recorded in the VCD header for VHDL ports shall be one of the following:

in, out, inout, internal, ports (includes in, out, and inout); the default is all ports

Note: The -direction argument is obsolete in ModelSim versions 5.5c and later. It is supported for backwards compatibility only. See Resimulating a VHDL design from a VCD file for information regarding its use in earlier versions.

See also

See Value Change Dump (VCD) Files chapter for more information on VCD files. Verilog tasks are documented in the IEEE 1364 standard.

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