Searching for binary signal values in the GUI

When you use the GUI to search for signal values displayed in 4-state binary radix, you should be aware of how ModelSim maps between binary radix and std_logic. The issue arises because there is no "uninitialized" value in binary, while there is in std_logic (designated by the letter "U"). Consequently, ModelSim relies on mapping tables to determine whether a match occurs between the displayed binary signal value and the underlying std_logic value.

For comparing VHDL std_logic/std_ulogic objects, ModelSim uses the table shown below. An entry of "0" in the table is "no match"; an entry of "1" is a "match"; an entry of "2" is a match only if you set the Tcl variable STDLOGIC_X_MatchesAnything to 1. Note that 'X' will match a 'U', and '-' will match anything.

Search Entry	Matches as follows:
	U	X	0	1	Z	W	L	H	-
U	1	1	0	0	0	0	0	0	1
X	1	1	2	2	2	2	2	2	1
0	0	2	1	0	0	0	1	0	1
1	0	2	0	1	0	0	0	1	1
Z	0	2	0	0	1	0	0	0	1
W	0	2	0	0	0	1	0	0	1
L	0	2	1	0	0	0	1	0	1
H	0	2	0	1	0	0	0	1	1
-	1	1	1	1	1	1	1	1	1

For comparing Verilog net values, ModelSim uses the table shown below. An entry of "2" is a match only if you set the Tcl variable "VLOG_X_MatchesAnything" to 1.

Search Entry	Matches as follows:
	0	1	Z	X
0	1	0	0	2
1	0	1	0	2
Z	0	0	1	2
X	2	2	2	1

Note: This matching algorithm applies only to searching via the GUI; it does not apply to VHDL or Verilog testbenches.

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