Interconnect delays

An interconnect delay represents the delay from the output of one device to the input of another. With Verilog designs, ModelSim can model single interconnect delays or multisource interconnect delays. See "Arguments, Verilog" under the vsim command for more information on the relevant command-line switches.

Per VHDL VITAL '95, there is no convenient way to handle interconnect delays from multiple outputs to a single input. Interconnect delay is modeled in the receiving device as a single delay from an input port to an internal node. (The node is explicitly declared.) The default is to use the value of the maximum encountered delay in the SDF file. Alternatively, you can choose the minimum or latest value of the multiple delays with the vsim command -multisource_delay option.

-multisource_delay min|max|latest 

Timing checks are performed on the interconnect delayed versions of input ports. This may result in misleading timing constraint violations, because the ports may satisfy the constraint while the delayed versions may not. If the simulator seems to report incorrect violations, be sure to account for the effect of interconnect delays.

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