Verilog SDF

Verilog designs can be annotated using either the simulator command-line options or the $sdf_annotate system task (also commonly used in other Verilog simulators). The command-line options annotate the design immediately after it is loaded, but before any simulation events take place. The $sdf_annotate task annotates the design at the time it is called in the Verilog source code. This provides more flexibility than the command-line options.

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