vgencomp

Once a Verilog module is compiled into a library, you can use the vgencomp command to write its equivalent VHDL component declaration to standard output. Optional switches allow you to generate bit or vl_logic port types; std_logic port types are generated by default.

Syntax

vgencomp

[-help] [-lib <library_name>] [-b] [-s] [-v] <module_name>

Arguments

-help

Displays the command's options and arguments. Optional.

-lib <library_name>

Specifies the pathname of the working library. If not specified, the default library work is used. Optional.

-b

Causes vgencomp to generate bit port types. Optional.

-s

Used for the explicit declaration of default std_logic port types. Optional.

-v

Causes vgencomp to generate vl_logic port types. Optional.

<module_name>

Specifies the name of the Verilog module to be accessed. Required.

Examples

This example uses a Verilog module that is compiled into the work library. The module begins as Verilog source code:

module top(i1, o1, o2, io1);
	parameter width = 8;
	parameter delay = 4.5;
	parameter filename = "file.in";

	input i1;
	output [7:0] o1;
	output [4:7] o2;
	inout [width-1:0] io1;
endmodule 

After compiling, vgencomp is invoked on the compiled module:

vgencomp top 

and writes the following to stdout:

component top  
    	generic(
		width           : integer := 8;
		delay           : real    := 4.500000;
		filename        : string  := "file.in"
			);
	port(
		i1              : in    std_logic;
		o1              : out   std_logic_vector(7 downto 0);
		o2              : out   std_logic_vector(4 to 7);
		io1             : inout std_logic_vector
		);
end component; 

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