A - B - C - D - E - F - G - H - I - J - K - L - M - N - O - P - Q - R - S - T - U - V - W - X - Y - Z

Symbols

+delay_mode_distributed
- Verilog-XL compatible compiler options

+delay_mode_path
- Verilog-XL compatible compiler options

+delay_mode_unit
- Verilog-XL compatible compiler options

+delay_mode_zero
- Verilog-XL compatible compiler options

+incdir+
- Verilog-XL compatible compiler options

+libext+
- Options supporting source libraries

+librescan
- Options supporting source libraries

+maxdelays
- Verilog-XL compatible compiler options

+mindelays
- Verilog-XL compatible compiler options

+nolibcell
- Options supporting source libraries

+nowarn
- Verilog-XL compatible compiler options

+typdelays
- Verilog-XL compatible compiler options

.main clear command
- .main clear

.so, shared object file

loading PLI/VPI applications
- Compiling and linking PLI/VPI applications

.wave.tree interrupt command
- .wave.tree interrupt

.wave.tree zoomfull command
- .wave.tree zoomfull

.wave.tree zoomin command
- .wave.tree zoomin

.wave.tree zoomlast command
- .wave.tree zoomlast

.wave.tree zoomout command
- .wave.tree zoomout

.wave.tree zoomrange command
- .wave.tree zoomrange

+define+
- Verilog-XL compatible compiler options

'delayed
- Signal attributes

Numerics

64-bit ModelSim

using with 32-bit FLI apps
- Using 64-bit ModelSim with 32-bit PLI/VPI Applications

A

abort command
- abort

Absolute time
- Simulation time units

ACC routines
- IEEE Std 1364 ACC routines

Accelerated packages
- Alternate IEEE libraries supplied

add button command
- add button

add list command
- add list

add wave command
- add wave

add_menu command
- add_menu

add_menucb command
- add_menucb

add_menuitem simulator command
- add_menuitem

add_separator command
- add_separator

add_submenu command
- add_submenu

alias command
- alias

architecture simulator state variable
- Simulator state variables

argc simulator state variable
- Simulator state variables

Arrays

indexes
- Indexing signals, memories, and nets

slices
- Indexing signals, memories, and nets

AssertFile .ini file variable
- [vsim] simulator control variables

AssertionFormat .ini file variable
- [vsim] simulator control variables

Assertions

selecting severity that stops simulation
- Assertion settings tab

B

Bad magic number error message
- Saving a simulation to a WLF file

balloon dialog

toggling on/off
- Setting Wave window display properties

Base (radix)

specifying in List window
- Editing and formatting HDL items in the List window

batch_mode command
- batch_mode

Batch-mode simulations
- Running command-line and batch-mode simulations
- Batch mode

stopping simulation
- when

bd (breakpoint delete) command
- bd

Binary radix

mapping to std_logic values
- Searching for binary signal values in the GUI

bookmark add wave command
- bookmark add wave

bookmark delete wave command
- bookmark delete wave

bookmark goto wave command
- bookmark goto wave

bookmark list wave command
- bookmark list wave

bookmarks
- Saving zoom range and scroll position with bookmarks

bp (breakpoint) command
- bp

Break

on assertion
- Assertion settings tab

on signal value
- when

BreakOnAssertion .ini file variable
- [vsim] simulator control variables

Breakpoints

continuing simulation after
- run

deleting
- Setting file-line breakpoints
- bd

enabling and disabling
- Setting breakpoints with the Edit > Breakpoints command

listing
- bp

setting
- Setting file-line breakpoints
- bp

signal breakpoints (when statements)
- Setting signal breakpoints

time-based
- Setting signal breakpoints

Time-based breakpoints in when statements
- when

viewing in the Source window
- Source window

Bus contention checking
- Bus contention checking

configuring
- check contention config

disabling
- check contention off

enabling
- check contention add

Bus float checking
- Bus float checking

configuring
- check float config

disabling
- check float off

enabling
- check float add

Busses, user-defined
- Combining signals into a user-defined bus

Button Adder (add buttons to windows)
- The Button Adder

Buttons

adding to the Main window button bar
- add button

C

case choice

must be locally static
- vcom

Case sensitivity

named port associations
- Named port associations

VHDL vs. Verilog
- Name case sensitivity

cd (change directory) command
- cd

Cell libraries
- Cell Libraries

change command
- change

change_menu_cmd command
- change_menu_cmd

check contention add command
- check contention add

check contention config command
- check contention config

check contention off command
- check contention off

check float add command
- check float add

check float config command
- check float config

check float off command
- check float off

check stable off command
- check stable off

check stable on command
- check stable on

checkpoint command
- checkpoint

Checkpoint/restore
- How to use checkpoint/restore

CheckpointCompressMode .ini file variable
- [vsim] simulator control variables

CheckSynthesis .ini file variable
- [vcom] VHDL compiler control variables

clear differences
- Compare menu

clocked comparison
- Clocked Compare
- Compare by Signal
- Compare by Region

Code Coverage

coverage clear command
- coverage clear

coverage reload command
- coverage reload

coverage report command
- coverage report

coverage_summary window
- The coverage_summary window

enabling code coverage
- Enabling Code Coverage
- Code Coverage commands

excluding lines/files
- Exclusions tab
- Excluding lines and files

invoking code coverage with vsim
- Invoking Code Coverage with Vsim

merging report files
- Merging coverage report files
- coverage reload

miss and exclusion details
- Misses tab

saving coverage reports
- The coverage_summary window menu bar

Tcl preference variables
- Code Coverage preference variables

Command reference
- Command reference

CommandHistory .ini file variable
- [vsim] simulator control variables

Command-line mode
- Running command-line and batch-mode simulations

commands

.main clear
- .main clear

.wave.tree interruptl
- .wave.tree interrupt

.wave.tree zoomfull
- .wave.tree zoomfull

.wave.tree zoomin
- .wave.tree zoomin

.wave.tree zoomlast
- .wave.tree zoomlast

.wave.tree zoomout
- .wave.tree zoomout

.wave.tree zoomrange
- .wave.tree zoomrange

abort
- abort

add button
- add button

add list
- add list

add wave
- add wave

add_menu
- add_menu

add_menucb
- add_menucb

add_menuitem
- add_menuitem

add_separator
- add_separator

add_submenu
- add_submenu

alias
- alias

batch_mode
- batch_mode

bd (breakpoint delete)
- bd

bookmark add wave
- bookmark add wave

bookmark delete wave
- bookmark delete wave

bookmark goto wave
- bookmark goto wave

bookmark list wave
- bookmark list wave

bp (breakpoint)
- bp

cd (change directory)
- cd

change
- change

change_menu_cmd
- change_menu_cmd

check contention add
- check contention add

check contention config
- check contention config

check contention off
- check contention off

check float add
- check float add

check float config
- check float config

check float off
- check float off

check stable off
- check stable off

check stable on
- check stable on

checkpoint
- checkpoint

compare annotate
- compare annotate
- compare configure

compare clock
- compare clock

compare close
- compare end

compare commands
- Waveform Comparison commands

compare delete
- compare delete

compare info
- compare info

compare list
- compare list

compare open
- compare start

compare optioins
- compare options

compare region
- compare add

compare reload
- compare reload

compare savediffs
- compare savediffs

compare saverules
- compare saverules

compare see
- compare see

compare start
- compare run

configure
- configure

coverage clear
- coverage clear

coverage reload
- coverage reload

coverage report
- coverage report

dataset alias
- dataset alias

dataset clear
- dataset clear

dataset close
- dataset close

dataset info
- dataset info

dataset list
- dataset list

dataset open
- dataset open

dataset rename
- dataset rename

delete
- delete

describe
- describe

disable_menu
- disable_menu

disable_menuitem
- disable_menuitem

disablebp
- disablebp

do
- do

down
- down

drivers
- drivers

dumplog64
- dumplog64

echo
- echo

edit
- edit

enable_menu
- enable_menu

enable_menuitem
- enable_menuitem

enablebp
- enablebp

environment
- environment

examine
- examine

exit
- exit

find
- find

force
- force

getactivecursortime
- getactivecursortime

getactivemarkertime
- getactivemarkertime

graphic interface commands
- Graphic interface commands

help
- help

history
- history

lecho
- lecho

left
- left

log
- log

lshift
- lshift

lsublist
- lsublist

macro_option
- macro_option

modelsim
- modelsim

next
- next

noforce
- noforce

nolog
- nolog

notation conventions
- Documentation conventions

notepad
- notepad

noview
- noview

nowhen
- nowhen

onbreak
- onbreak

onElabError
- onElabError

onerror
- onerror

pause
- pause

play
- play

power add
- power add

power report
- power report

power reset
- power reset

printenv
- printenv

profile clear
- profile clear

profile interval
- profile interval

profile off
- profile off

profile on
- profile on

profile option
- profile option

profile report
- profile report

property list
- property list

property wave
- property wave

pwd
- pwd

quietly
- quietly

quit
- quit

radix
- radix

record
- record

report
- report

restart
- restart

restore
- restore

resume
- resume

right
- right

run
- run

search
- search

searchlog
- searchlog

seetime
- seetime

shift
- shift

show
- show

splitio
- splitio

status
- status

step
- step

stop
- stop

system
- System commands

tb (traceback)
- tb

toggle add
- toggle add

toggle report
- toggle report

toggle reset
- toggle reset

transcribe
- transcribe

transcript
- transcript

TreeUpdate
- write format

tssi2mti
- tssi2mti

up
- up

variables referenced in
- ModelSim variables

vcd add
- vcd add

vcd checkpoint
- vcd checkpoint

vcd comment
- vcd comment

vcd dumpports
- vcd dumpports

vcd dumpportsall
- vcd dumpportsall

vcd dumpportsflush
- vcd dumpportsflush

vcd dumpportslimit
- vcd dumpportslimit

vcd dumpportsoff
- vcd dumpportsoff

vcd dumpportson
- vcd dumpportson

vcd file
- vcd file

vcd files
- vcd files

vcd flush
- vcd flush

vcd limit
- vcd limit

vcd off
- vcd off

vcd on
- vcd on

vcom
- vcom

vdel
- vdel

vdir
- vdir

vgencomp
- vgencomp

view
- view

virtual count
- virtual count

virtual define
- virtual define

virtual delete
- virtual delete

virtual describe
- virtual describe

virtual expand
- virtual expand

virtual function
- virtual function

virtual hide
- virtual hide

virtual log
- virtual log

virtual nohide
- virtual nohide

virtual nolog
- virtual nolog

virtual region
- virtual region

virtual save
- virtual save

virtual show
- virtual show

virtual signal
- virtual signal

virtual type
- virtual type

vlib
- vlib

vlog
- vlog

vmake
- vmake

vmap
- vmap

vsim
- vsim

VSIM Tcl commands
- ModelSim Tcl commands

vsimDate
- vsim<info>

vsimId
- vsim<info>

vsimVersion
- vsim<info>

WaveActivateNextPane
- write format

WaveRestoreCursors
- write format

WaveRestoreZoom
- write format

when
- when

where
- where

wlf2log
- wlf2log

write format
- write format

write list
- write list

write preferences
- write preferences

write report
- write report

write transcript
- write transcript

write tssi
- write tssi

write wave
- write wave

Comment characters in VSIM commands
- Documentation conventions

compare

add clock
- Compare by Signal

add region
- Compare by Region

add signals
- Adding Signals, Regions and/or Clocks

by signal
- Compare by Signal

clear differences
- Compare menu

clocked
- Clocked Compare
- Compare by Signal
- Compare by Region

continuous
- Continuous Compare
- Compare by Signal
- Compare by Region

difference markers
- Wave window display

differences
- Printing compare differences

end
- Compare menu

graphic interface
- Graphic Interface to Waveform Comparison

icons
- Compare icons

limit count
- Setting Compare Options

list window display
- List window display

menu
- Compare menu

modes
- Two Modes of Comparison

modify clock
- Compare by Signal

options
- Setting Compare Options

pathnames
- Wave window display

preference variables
- Waveform Comparison preference variables

reference dataset
- Reference Dataset

reference region
- Compare by Region

reload
- Compare menu

rules
- Compare menu

run
- Compare menu

save differences
- Compare menu

show differences
- Compare menu

signal options
- Compare by Signal

specify dataset
- Test Dataset

specify when expression
- Compare by Signal

start
- Compare menu

startup wizard
- Compare menu

tab
- Test Dataset

test dataset
- Test Dataset

test region
- Compare by Region

timing differences
- Wave window display

tolerance
- Compare by Signal
- Compare by Region

tolerances
- Continuous Compare

values
- Wave window display

verilog matching
- Setting Compare Options

VHDL matching
- Setting Compare Options

wave window display
- Wave window display

waveforms
- Waveform Comparison

wizard
- Compare menu

write report
- Compare menu

compare annotate command
- compare annotate
- compare configure

compare by region
- Compare by Region

compare clock command
- compare clock

compare close command
- compare end

compare commands
- Waveform Comparison commands

compare delete command
- compare delete

compare info command
- compare info

compare list command
- compare list

compare open command
- compare start

compare options command
- compare options

compare region command
- compare add

compare reload command
- compare reload

compare savediffs command
- compare savediffs

compare saverules command
- compare saverules

compare see command
- compare see

compare simulations
- WLF files (datasets) and virtuals

compare start command
- compare run

Compiler directives
- Compiler Directives

IEEE Std 1364-2000
- IEEE Std 1364 compiler directives

XL compatible compiler directives
- Verilog-XL compatible compiler directives

Compiling

locating source errors
- Locating source errors during compilation

range checking in VHDL
- Range and index checking
- vcom

setting default options
- Setting default compile options

setting options in projects
- Setting compiler options

setting order in projects
- Changing compile order

Verilog
- Compilation
- vlog

including library components
- vlog

incremental compilation
- Incremental compilation

optimizing performance
- Compiling for faster performance
- vlog

XL 'uselib compiler directive
- Verilog-XL `uselib compiler directive

XL compatible options
- Verilog-XL compatible compiler options

VHDL
- Compiling VHDL designs
- vcom

at a specified line number (-line <number>)
- vcom

selected design units (-just eapbc)
- vcom

standard package (-s)
- vcom

with the graphic interface
- Compiling with the graphic interface

with VITAL packages
- Compiling and Simulating with accelerated VITAL packages

Component declaration

generating VHDL from Verilog
- vgencomp component declaration

with vgencomp
- vgencomp component declaration

concatenation

directives
- Concatenation of signals or subelements

of signals
- virtual signal
- Concatenation of signals or subelements

ConcurrentFileLimit .ini file variable
- [vsim] simulator control variables

configuration simulator state variable
- Simulator state variables

Configurations

simulating
- vsim

configure command
- configure

Constants

displaying values of
- describe
- examine

constants

used in case statements
- vcom

context menus

coverage_source window
- Excluding lines and files

described
- Context menus

Library page
- Managing library contents

Signal window
- Setting signal breakpoints

Structure pages
- Viewing dataset structure

continuous comparison
- Continuous Compare
- Compare by Signal

convert real to time
- to_time()

convert time to real
- to_real()

coverage clear command
- coverage clear

coverage reload command
- coverage reload

coverage report command
- coverage report

coverage_summary window
- The coverage_summary window

cursors

link to Dataflow window
- Link to active cursor in Wave window

Wave window
- Using time cursors in the Wave window

Customizing

adding buttons
- add button

the interface
- Customizing the interface

via preference variables
- Preference variables located in Tcl files

D

Dataflow window
- Dataflow window

dataset alias command
- dataset alias

Dataset Browser
- Managing datasets

dataset clear command
- dataset clear

dataset close command
- dataset close

dataset info command
- dataset info

dataset list command
- dataset list

dataset open command
- dataset open

dataset rename command
- dataset rename

datasets
- WLF files (datasets) and virtuals
- Introduction

managing
- Managing datasets

reference
- Reference Dataset

restrict dataset prefix display
- Restricting the dataset prefix display

simulator time resolution
- WLF files (datasets)

specifying for compare
- Test Dataset

specifying with the environment command
- environment

test
- Test Dataset

DatasetSeparator .ini file variable
- [vsim] simulator control variables

Declarations

hiding implicit with explicit declarations
- vcom

Default compile options
- Setting default compile options

Default editor

changing
- Environment variables

DefaultForceKind .ini file variable
- [vsim] simulator control variables

DefaultRadix .ini file variable
- [vsim] simulator control variables

DefaultRestartOptions variable
- [vsim] simulator control variables
- Restart command defaults

Defaults

restoring
- Returning to the original ModelSim defaults

window arrangement
- Saving window layout

Delay

detecting infinite zero-delay loops
- Detecting infinite zero-delay loops

interconnect
- Verilog-XL compatible simulator options
- vsim
- vsim

modes for Verilog models
- Delay modes

SDF files
- Standard Delay Format (SDF) Timing Annotation

specifying stimulus delay
- Forcing signal and net values

DelayFileOpen .ini file variable
- [vsim] simulator control variables

delete command
- delete

deleting library contents
- Managing library contents

Delta

collapse deltas in the List window
- Trigger settings tab

hide deltas in the List window
- Trigger settings tab
- configure

referencing simulator iteration

as a simulator state variable
- Simulator state variables

Delta cycles
- Detecting infinite zero-delay loops

delta simulator state variable
- Simulator state variables

Dependent design units
- Dependency checking

describe command
- describe

Descriptions of HDL items
- Checking HDL item values and descriptions

Design hierarchy

viewing in Structure window
- Structure window

Design library

assigning a logical name
- Assigning a logical name to a design library

creating
- Working with design libraries

for VHDL design units
- Compiling VHDL designs

mapping search rules
- Library search rules

resource type
- Design library types

working type
- Design library types

Design stability checking
- Design stability checking

Design units
- Design library contents

adding Verilog units to a library
- vlog

report of units simulated
- write report

viewing hierarchy
- Tree window hierarchical view

Directories

mapping libraries
- vmap

moving libraries
- Moving a library

disable_menu command
- disable_menu

disable_menuitem command
- disable_menuitem

disablebp command
- disablebp

DLL files

loading
- Compiling and linking PLI/VPI applications

do command
- do

DO files (macros)

error handling
- Using Parameters with DO files

executing at startup
- Environment variables
- [vsim] simulator control variables

passing parameters to
- Using Parameters with DO files

Tcl source command
- Using Parameters with DO files

Do files (macros)
- do

documentation
- Where to find our documentation

DOPATH environment variable
- Environment variables

down command
- down

drivers command
- drivers

dumplog64 command
- dumplog64

dumpports tasks

VCD files
- ModelSim VCD commands and VCD tasks

E

echo command
- echo

edit command
- edit

Editing

in notepad windows
- Mouse and keyboard shortcuts
- Mouse and keyboard shortcuts in Main and Source windows

in the Main window
- Mouse and keyboard shortcuts
- Mouse and keyboard shortcuts in Main and Source windows

in the Source window
- Mouse and keyboard shortcuts
- Mouse and keyboard shortcuts in Main and Source windows

Editor

changing default
- Environment variables

EDITOR environment variable
- Environment variables

enable_menu command
- enable_menu

enable_menuitem command
- enable_menuitem

enablebp command
- enablebp

encryption

securing pre-compiled libraries
- Source code security and -nodebug

end comparison
- Compare menu

ENDFILE function
- The ENDFILE function

ENDLINE function
- The ENDLINE function

Entities

selecting for simulation
- vsim

entity simulator state variable
- Simulator state variables

Environment

displaying or changing pathname
- environment

environment command
- environment

Environment variables
- Environment variables

accessed during startup
- Environment variables accessed during startup

for locating license file
- Starting the license server daemon

referencing from ModelSim command line
- Referencing environment variables within ModelSim

referencing with VHDL FILE variable
- Referencing environment variables within ModelSim

setting in Windows
- Creating environment variables in Windows

specify transcript file location with TranscriptFile
- [vsim] simulator control variables

specifying library locations in modelsim.ini file
- [Library] library path variables

specifying UNIX editor
- edit

used in Solaris linking for FLI
- 32-bit Solaris platform

using in pathnames
- Environment variables and pathnames

using with location mapping
- Using location mapping

variable substitution using Tcl
- Variable substitution

viewing current names and values with printenv
- printenv

Error messages

bad magic number
- Saving a simulation to a WLF file

Errors

during compilation, locating
- Locating source errors during compilation

onerror command
- onerror

Event order

issues between simuators
- Event order issues

event order

changing in Verilog
- vlog

examine command
- examine

exclusion filter
- Exclusions tab

exit command
- exit

Explicit .ini file variable
- [vcom] VHDL compiler control variables

Expression Builder
- The GUI Expression Builder
- Compare by Region

specify when expression
- Compare by Signal
- Compare by Region
- Compare by Region

Expression_format
- GUI_expression_format

Extended identifier
- VHDL and Verilog identifiers

extended identifiers

syntax in commands
- Extended identifiers

F

-f
- Verilog-XL compatible compiler options

F8 function key
- Mouse and keyboard shortcuts
- Mouse and keyboard shortcuts in Main and Source windows

feature names

described
- Feature names

file-line breakpoints
- Setting file-line breakpoints

find command
- find

Finding

a cursor in the Wave window
- Finding a cursor

a marker in the List window
- Finding a marker

names and values
- Finding names, searching for values, and locating cursors

FLEXlm license manager
- Using the FLEXlm License Manager
- Administration tools for Windows

administration tools for Windows
- Administration tools for Windows

license server utilities
- License administration tools

FLI
- Foreign language interface

force command
- force

defaults
- Force command defaults

foreign language interface
- Foreign language interface

format file

Wave window
- Adding HDL items in the Wave window

format list
- write format

format wave
- write format

G

GenerateFormat .ini file variable
- [vsim] simulator control variables

Generics

assigning or overriding values with -g and -G
- vsim

examining generic values
- examine

VHDL
- VHDL generics

get_resolution() VHDL function
- get_resolution()

getactivecursortime command
- getactivecursortime

getactivemarkertime command
- getactivemarkertime

Graphic interface
- Graphic Interface
- Customizing the interface

UNIX support
- ModelSim graphic interface

waveform comparison
- Graphic Interface to Waveform Comparison

GUI_expression_format
- GUI_expression_format

GUI expression builder
- The GUI Expression Builder

syntax
- Expression syntax

H

halting waveform drawing
- .wave.tree interrupt

Hardware Model interface
- VHDL Hardware Model interface

Hazard .ini file variable (VLOG)
- [vlog] Verilog compiler control variables

Hazards

event order issues
- Event order issues

HDL item
- What is an "HDL item"

help command
- help

Hierarchical profile
- Viewing Performance Analyzer Results

Hierarchy

referencing signals in
- init_signal_spy()

viewing signal names without
- Setting Wave window display properties

history command
- history

History shortcuts
- Command history shortcuts
- Command history shortcuts

hm_entity
- Creating foreign architectures with hm_entity

HOME environment variable
- Environment variables

I

ieee .ini file variable
- [Library] library path variables

IEEE libraries
- Alternate IEEE libraries supplied

IEEE Std 1076
- Standards supported
- VHDL Simulation

IEEE Std 1364
- Standards supported
- Verilog Simulation

ieee_synopsis library
- Alternate IEEE libraries supplied

IgnoreError .ini file variable
- [vsim] simulator control variables

IgnoreFailure .ini file variable
- [vsim] simulator control variables

IgnoreNote .ini file variable
- [vsim] simulator control variables

IgnoreVitalErrors .ini file variable
- [vcom] VHDL compiler control variables

IgnoreWarning .ini file variable
- [vsim] simulator control variables

Implicit operator, hiding with vcom -explicit
- vcom

Incremental compilation

automatic
- Incremental compilation

manual
- Incremental compilation

with Verilog
- Incremental compilation

index checking
- Range and index checking

Indexing signals, memories and nets
- Indexing signals, memories, and nets

init_signal_spy
- init_signal_spy()

init_usertfs function
- Registering PLI applications

initial dialog box

turning on/off
- Personal preferences

Initialization sequence
- Initialization sequence

Installation

locating the license file
- Starting the license server daemon

Instantiation in mixed-language design

Verilog from VHDL
- VHDL instantiation of Verilog design units

VHDL from Verilog
- Verilog instantiation of VHDL design units

Instantiation label
- Instance name components in the Structure window

Interconnect delays
- Verilog-XL compatible simulator options
- Interconnect delays
- vsim

internal signals

adding to a VCD file
- vcd add

Iteration_limit

detecting infinite zero-delay loops
- Detecting infinite zero-delay loops

IterationLimit .ini file variable
- [vsim] simulator control variables

K

Keyboard shortcuts

List window
- List window keyboard shortcuts
- List window keyboard shortcuts

Main window
- Mouse and keyboard shortcuts
- Mouse and keyboard shortcuts in Main and Source windows

Source window
- Mouse and keyboard shortcuts in Main and Source windows

Wave window
- Wave window mouse and keyboard shortcuts
- Wave window mouse and keyboard shortcuts

L

lecho command
- lecho

left command
- left

Libraries

64-bit and 32-bit in same library
- Maintaining 32-bit and 64-bit versions in the same library

alternate IEEE libraries
- Alternate IEEE libraries supplied

creating design libraries
- Working with design libraries
- vlib

design library types
- Design library types

design units
- Design library contents

ieee_numeric
- Alternate IEEE libraries supplied

ieee_numeric library
- Alternate IEEE libraries supplied

ieee_synopsis
- Alternate IEEE libraries supplied

including precompiled modules
- Libraries settings tab
- vlog

listing contents
- vdir

lock file, unlocking
- vcom
- vlog

mapping

from the command line
- Library mapping from the command line

from the GUI
- Library mappings with the GUI

hierarchically
- Hierarchical library mapping

search rules
- Library search rules

modelsim_lib
- Util package

moving
- Moving a library

naming
- Assigning a logical name to a design library

predefined
- Predefined libraries

refreshing library images
- Regenerating your design libraries
- vcom
- vlog

resource libraries
- Design library types

setting up for groups
- Setting up libraries for group use

std
- Predefined libraries

verilog
- Library usage
- VHDL and Verilog ports

VHDL library clause
- Specifying the resource libraries

working libraries
- Design library types

working with contents of
- Managing library contents

library simulator state variable
- Simulator state variables

Licensing

feature name descriptions
- Feature names

License variable in .ini file
- [vsim] simulator control variables

locating the license file
- Starting the license server daemon

using the FLEXlm license manager
- Using the FLEXlm License Manager

List window
- List window

adding items to
- add list

waveform comparison
- List window display

LM_LICENSE_FILE environment variable
- Environment variables

lmdown license server utility
- lmdown

lmgrd license server utility
- lmdown

lmremove license server utility
- lmremove

lmreread license server utility
- lmreread

lmstat license server utility
- License administration tools

lmutil license server utility
- Administration tools for Windows

Locating source errors during compilation
- Locating source errors during compilation

Location maps

referencing source files
- Referencing source files with location maps

Locked memory

under HP-UX 10.2
- Improve performance by locking memory on HP-UX 10.2

under Solaris
- Improve performance of large simulations on Sun/Solaris

LockedMemory .ini file variable
- [vsim] simulator control variables

log command
- log

Log file

log command
- log

nolog command
- nolog

overview
- WLF files (datasets) and virtuals

QuickSim II format
- wlf2log

redirecting with -l
- vsim

virtual log command
- virtual log

virtual nolog command
- virtual nolog

Logic Modeling

SmartModel

command channel
- Command channel

SmartModel Windows

lmcwin commands
- SmartModel lmcwin commands

memory arrays
- Memory arrays

lshift command
- lshift

lsublist command
- lsublist

M

macro_option command
- macro_option

MacroNestingLevel simulator state variable
- Simulator state variables

Macros (DO files)

creating from a saved transcript
- Saving the Main window transcript file

depth of nesting, simulator state variable
- Simulator state variables

DO files (macros)
- Macros (DO files)

error handling
- Using Parameters with DO files

executing
- do

executing at breakpoints
- bp

forcing signals, nets, or registers
- force

parameter as a simulator state variable (n)
- Simulator state variables

parameter total as a simulator state variable
- Simulator state variables

passing parameters to
- Using Parameters with DO files
- do

relative directories
- do

shifting parameter values
- shift

startup macros
- Using a startup file

Main window
- Main window

Mapping libraries

from the command line
- Library mapping from the command line

hierarchically
- Hierarchical library mapping

Mapping Verilog states in mixed designs
- Verilog states

math_complex package
- Alternate IEEE libraries supplied

math_real package
- Alternate IEEE libraries supplied

Memory

enabling shared memory on Sun/Solaris
- Improve performance of large simulations on Sun/Solaris

locked memory under HP-UX 10.2
- Improve performance by locking memory on HP-UX 10.2

modeling in VHDL
- Modeling memory in VHDL

Menus

customizing menus and buttons
- Customizing menus and buttons

Dataflow window
- Dataflow window menu bar

List window
- The List window menu bar

Main window
- The Main window menu bar

Process window
- The Process window menu bar

Signals window
- The Signals window menu bar

Source window
- The Source window menu bar

Structure window
- The Structure window menu bar

tearing off or pinning menus
- Menu tear off

Variables window
- The Variables window menu bar

Wave window
- The Wave window menu bar

Messages

bad magic number
- Saving a simulation to a WLF file

echoing
- echo

redirecting
- [vsim] simulator control variables

turning off assertion messages
- Turning off assertion messages

turning off warnings from arithmetic packages
- Turning off warnings from arithmetic packages

MGC_LOCATION_MAP variable
- Environment variables

Miss and Exclusion details
- Misses tab

Mixed-language simulation
- Mixed VHDL and Verilog Designs

mnemonics

assigning to signal values
- virtual type

MODEL_TECH environment variable
- Environment variables

MODEL_TECH_TCL environment variable
- Environment variables

Modeling memory in VHDL
- Modeling memory in VHDL

ModelSim

custom setup with daemon options
- Format of the daemon options file

license file
- Starting the license server daemon

modelsim command
- modelsim

ModelSim commands
- Commands
- wlf2log

comments in commands
- Documentation conventions

MODELSIM environment variable
- Environment variables

modelsim.ini

default to VHDL93
- VHDL93

hierarchial library mapping
- Hierarchical library mapping

opening VHDL files
- Opening VHDL files

setting restart command defaults
- Restart command defaults

to specify a startup file
- Using a startup file

turning off arithmetic warnings
- Turning off warnings from arithmetic packages

turning off assertion messages
- Turning off assertion messages

using environment variables in
- Commonly used INI variables

using to create a transcript file
- Creating a transcript file

using to define force command default
- Force command defaults

using to delay file opening
- Opening VHDL files

modelsim.tcl file
- Preference variables located in Tcl files

modelsim_lib
- Util package

MODELSIM_TCL environment variable
- Environment variables

Mouse shortcuts

Main window
- Mouse and keyboard shortcuts
- Mouse and keyboard shortcuts in Main and Source windows

Source window
- Mouse and keyboard shortcuts in Main and Source windows

Wave window
- Wave window mouse and keyboard shortcuts
- Wave window mouse and keyboard shortcuts

MPF file

loading from the command line
- Accessing projects from the command line

MTI_TF_LIMIT environment variable
- Environment variables

Multiple drivers on unresolved signal
- Setting default compile options

multiple simulations
- WLF files (datasets) and virtuals

multi-source interconnect delays
- vsim

N

n simulator state variable
- Simulator state variables

Name case sensitivity

VHDL vs. Verilog
- Name case sensitivity

Names

alternative signal names in the List window (-label)
- add list

alternative signal names in the Wave window (-label)
- add wave

Negative pulses

driving an error state
- Verilog-XL compatible simulator options
- vsim

negative timing checks
- Verilog-XL compatible system tasks

Nets

adding to the Wave and List windows
- Adding HDL items to the Wave and List windows or a WLF file

applying stimulus to
- force

displaying drivers of
- drivers

displaying in Dataflow window
- Dataflow window

displaying values in Signals window
- Signals window

examining values
- examine

forcing signal and net values
- Forcing signal and net values

saving values as binary log file
- Adding HDL items to the Wave and List windows or a WLF file

viewing waveforms
- Wave window

New features
- What's new in ModelSim

Next and previous edges, finding
- Wave window mouse and keyboard shortcuts
- left
- right
- Wave window mouse and keyboard shortcuts

next command
- next

No space in time literal
- Setting default compile options

NoCaseStaticError .ini file variable
- [vcom] VHDL compiler control variables

NoDebug .ini file variable (VCOM)
- [vcom] VHDL compiler control variables

NoDebug .ini file variable (VLOG)
- [vlog] Verilog compiler control variables

noforce command
- noforce

NoIndexCheck .ini file variable
- [vsim] simulator control variables

nolog command
- nolog

NoOthersStaticError .ini file variable
- [vcom] VHDL compiler control variables

notepad command
- notepad

Notepad windows, text editing
- Mouse and keyboard shortcuts
- Mouse and keyboard shortcuts in Main and Source windows

noview command
- noview

NoVital .ini file variable
- [vcom] VHDL compiler control variables

NoVitalCheck .ini file variable
- [vcom] VHDL compiler control variables

Now simulator state variable
- Simulator state variables

now simulator state variable
- Simulator state variables

special considerations
- Special considerations for $now

nowhen command
- nowhen

numeric_bit package
- Alternate IEEE libraries supplied

numeric_std package
- Alternate IEEE libraries supplied

NumericStdNoWarnings .ini file variable
- [vsim] simulator control variables

O

onbreak command
- onbreak

onElabError command
- onElabError

onerror command
- onerror

Operating systems supported
- ModelSim graphic interface

Optimize for std_logic_1164
- Setting default compile options

Optimize_1164 .ini file variable
- [vcom] VHDL compiler control variables

Optimizing Verilog with -fast
- Compiling for faster performance

without source
- Using pre-compiled libraries

order of event

changing in Verilog
- vlog

order of events

issues
- Event order issues

P

Packages

standard
- Predefined libraries

textio
- Predefined libraries

util
- Util package

vital_memory
- VITAL 2000 library

Parameters, using with macros
- Using Parameters with DO files

Pathnames
- Wave window display

pathnames

dealing with spaces
- File and directory pathnames

Pathnames in VSIM commands
- HDL item pathnames

PathSeparator .ini file variable
- [vsim] simulator control variables

pause command
- pause

Performance

enabling shared memory
- Improve performance of large simulations on Sun/Solaris

improving for Verilog simulations
- Compiling for faster performance

improving on HP-UX 10.2
- Improve performance by locking memory on HP-UX 10.2

improving on Sun/Solaris
- Improve performance of large simulations on Sun/Solaris

Performance Analyzer
- Performance Analyzer

%parent field
- Differences in the Ranked and Hierarchical Views

commands
- Performance Analyzer commands

getting started
- Getting Started

hierarchical profile
- Viewing Performance Analyzer Results

in(%) field
- Interpreting the Under(%) and In(%) Fields

interpreting data
- Interpreting the data

name field
- Interpreting the Name Field

profile report command
- The report option

ranked profile
- Differences in the Ranked and Hierarchical Views

report option
- The report option

setting preferences
- Performance Analyzer preference variables

statistical sampling
- A Statistical Sampling Profiler

under(%) field
- Interpreting the Under(%) and In(%) Fields

view_profile command
- Viewing Performance Analyzer Results

view_profile_ranked command
- Viewing Performance Analyzer Results

viewing results
- Viewing Performance Analyzer Results

Platforms, supported
- ModelSim graphic interface

play command
- play

PLI

specifying which apps to load
- Registering PLI applications

Veriuser entry
- Registering PLI applications

PLI/VPI
- Verilog PLI/VPI

tracing
- PLI/VPI tracing

PLIOBJS environment variable
- Registering PLI applications
- Environment variables

Popup

toggling Waveform popup on/off
- Waveform pane
- Setting Wave window display properties
- Wave window display

port driver data

capturing
- Capturing port driver data

Ports

VHDL and Verilog
- VHDL and Verilog ports

Postscript

saving a waveform in
- Printing and saving waveforms

power add command
- power add

power report command
- power report

power reset command
- power reset

Precedence

of variables
- Variable precedence

Pre-compilied libraries

optimizing with -fast
- Using pre-compiled libraries

pref.tcl file
- Preference variables located in Tcl files

Preference variables

code coverage
- Code Coverage preference variables

editing
- Preference variables located in Tcl files

located in .ini files
- Preference variables located in INI files

located in Tcl files
- Preference variables located in Tcl files

performance analyzer
- Performance Analyzer preference variables

waveform compare
- Waveform Comparison preference variables

printenv command
- printenv

printing

comparison differences
- Printing compare differences

waveforms in the Wave window
- Printing and saving waveforms

Process window
- Process window

Process without a wait statement
- Setting default compile options

Processes

displayed in Dataflow window
- Dataflow window

values and pathnames in Variables window
- Variables window

profile clear command
- profile clear

profile interval command
- profile interval

profile off command
- profile off

profile on command
- profile on

profile option command
- profile option

profile report command
- The report option
- profile report

Profiler, see Performance Analyzer
- Performance Analyzer

Programming Language Interface
- Verilog PLI/VPI

projects

accessing from the command line
- Accessing projects from the command line

adding files to
- Step 2 - Add files to the project

changing compile order
- Changing compile order

compiling the files
- Step 3 - Compile the files

creating
- Step 1 - Create a new project

customizing settings
- Customizing project settings

differences in 5.5
- How do projects differ in version 5.5?

loading a design
- Step 4 - Simulate a design

MODELSIM environment variable
- Environment variables

override mapping for work directory with vcom
- vcom

override mapping for work directory with vlog
- vlog

overview
- Introduction

setting compiler options in
- Setting compiler options

propagation

preventing X propagation
- vsim

property list command
- property list

property wave command
- property wave

'protect compiler directive
- vcom
- vlog
- Source code security and -nodebug

Pulse error state
- Verilog-XL compatible simulator options
- vsim

pwd command
- pwd

Q

QuickSim II logfile format
- wlf2log

Quiet .ini file variable

VCOM
- [vcom] VHDL compiler control variables

VLOG
- [vlog] Verilog compiler control variables

quietly command
- quietly

quit command
- quit

R

-R
- Options supporting source libraries

Radix

changing in Signals, Variables, Dataflow, List, and Wave windows
- radix

of signals being examined
- examine

of signals in Wave window
- add wave

specifying in List window
- Editing and formatting HDL items in the List window

specifying in Signals window
- Forcing signal and net values

user-defined character strings
- virtual type

radix command
- radix

range checking
- Range and index checking

disabling
- vcom

enabling
- vcom

RangeCheck .ini file variable
- [vsim] simulator control variables

Ranked profile
- Differences in the Ranked and Hierarchical Views

real type

converting to time
- to_time()

Rebuilding supplied libraries
- Rebuilding supplied libraries

Reconstruct RTL-level design busses
- Virtual signals

record command
- record

Records

changing values of
- Variables window

Redirecting messages

TranscriptFile
- [vsim] simulator control variables

reference region
- Compare by Region

reference signals
- Introduction

Refreshing library images
- Regenerating your design libraries
- vcom
- vlog

Register variables

adding to the Wave and List windows
- Adding HDL items to the Wave and List windows or a WLF file

displaying values in Signals window
- Signals window

saving values as binary log file
- Adding HDL items to the Wave and List windows or a WLF file

viewing waveforms
- Wave window

report command
- report

RequireConfigForAllDefaultBinding variable
- [vcom] VHDL compiler control variables

Resolution
- Selecting the time resolution
- get_resolution()

specifying with -t argument
- vsim

Resolution .ini file variable
- [vsim] simulator control variables

resolution simulator state variable
- Simulator state variables

Resource library
- Design library types

Restart
- Run menu
- The Main window toolbar
-

restart command
- restart

defaults
- Restart command defaults

restore command
- restore

Restoring defaults
- Returning to the original ModelSim defaults

Results

saving simulations
- WLF files (datasets) and virtuals

resume command
- resume

right command
- right

run command
- run

RunLength .ini file variable
- [vsim] simulator control variables

S

save differences
- Compare menu

Saving and viewing waveforms
- WLF files (datasets) and virtuals

ScalarOpts .ini file variable
- [vcom] VHDL compiler control variables
- [vlog] Verilog compiler control variables

SDF

errors and warnings
- Errors and warnings

instance specification
- Instance specification

interconnect delays
- Interconnect delays

mixed VHDL and Verilog designs
- SDF for Mixed VHDL and Verilog Designs

specification with the GUI
- SDF specification with the GUI

troubleshooting
- Troubleshooting

Verilog

$sdf_annotate system task
- The $sdf_annotate system task

optional conditions
- Optional conditions

optional edge specifications
- Optional edge specifications

rounded timing values
- Rounded timing values

SDF to Verilog construct matching
- SDF to Verilog construct matching

VHDL

Resolving errors
- Resolving errors

SDF to VHDL generic matching
- SDF to VHDL generic matching

search command
- search

Searching

binary signal values in the GUI
- Searching for binary signal values in the GUI

List window

signal values, transitions, and names
- Finding items by name in the List window
- down
- up
- GUI_expression_format

next and previous edge in Wave window
- left
- right

values and names
- Finding names, searching for values, and locating cursors

Verilog libraries
- Library usage

waveform

signal values, edges and names
- Finding and replacing in the Source window
- Finding items in the Structure window
- Finding items by name or value in the Wave window
- left
- right

searchlog command
- searchlog

seetime command
- seetime

sequencing

differences in event order
- Event order issues

Shared memory

improving performance on HP-UX 10.2
- Improve performance by locking memory on HP-UX 10.2

improving performance on Sun/Solaris
- Improve performance of large simulations on Sun/Solaris

Shared objects

loading FLI applications

see ModelSim FLI Reference manual
- Compiling and linking PLI/VPI applications

loading PLI/VPI applications
- Compiling and linking PLI/VPI applications

shift command
- shift

Shortcuts

command history
- Command history shortcuts
- Command history shortcuts

command line caveat
- Command shortcuts
- Command shortcuts

List window
- List window keyboard shortcuts
- List window keyboard shortcuts

Main window
- Mouse and keyboard shortcuts in Main and Source windows

Main windows
- Mouse and keyboard shortcuts

Source window
- Mouse and keyboard shortcuts in Main and Source windows

text editing
- Mouse and keyboard shortcuts
- Mouse and keyboard shortcuts in Main and Source windows

Wave window
- Wave window mouse and keyboard shortcuts
- Wave window mouse and keyboard shortcuts

show command
- show

show differences
- Compare menu

Show source lines with errors
- Setting default compile options

Show_source .ini file variable

VCOM
- [vcom] VHDL compiler control variables

VLOG
- [vlog] Verilog compiler control variables

Show_VitalChecksWarning .ini file variable
- [vcom] VHDL compiler control variables

Show_Warning1 .ini file variable
- [vcom] VHDL compiler control variables

Show_Warning2 .ini file variable
- [vcom] VHDL compiler control variables

Show_Warning3 .ini file variable
- [vcom] VHDL compiler control variables

Show_Warning4 .ini file variable
- [vcom] VHDL compiler control variables

Show_Warning5 .ini file variable
- [vcom] VHDL compiler control variables

signal breakpoints
- Setting signal breakpoints

Signal names

viewing without hierarchy
- Setting Wave window display properties

Signal spy
- init_signal_spy()

Signal transitions

searching for
- Zooming - changing the waveform display range

Signals

adding to a WLF file
- Adding HDL items to the Wave and List windows or a WLF file

adding to the Wave and List windows
- Adding HDL items to the Wave and List windows or a WLF file

alternative names in the List window (-label)
- add list

alternative names in the Wave window (-label)
- add wave

applying stimulus to
- Forcing signal and net values
- force

combining into a user-defined bus
- Combining signals into a user-defined bus

creating a signal log file
- log

displaying drivers of
- drivers

displaying environment of
- environment

displaying in Dataflow window
- Dataflow window

displaying values in Signals window
- Signals window

examining values
- examine

finding
- find

indexing arrays
- Indexing signals, memories, and nets

pathnames in VSIM commands
- HDL item pathnames

referencing in the hierarchy
- init_signal_spy()

replacing values of with text
- virtual type

saving values as binary log file
- Adding HDL items to the Wave and List windows or a WLF file

selecting signal types to view
- Selecting HDL item types to view

specifying force time
- force

specifying radix of in List window
- add list

specifying radix of in Wave window
- add wave

specifying radix of signal to examine
- examine

viewing waveforms
- Wave window

Signals window
- Signals window

Simulating

applying stimulus to signals and nets
- Forcing signal and net values

batch mode
- Running command-line and batch-mode simulations

command-line mode
- Running command-line and batch-mode simulations

comparing simulations
- WLF files (datasets) and virtuals
- Waveform Comparison

mixed Verilog and VHDL Designs

compilers
- Separate compilers, common libraries

libraries
- Separate compilers, common libraries

Verilog parameters
- Verilog parameters

Verilog state mapping
- Verilog states

VHDL and Verilog ports
- VHDL and Verilog ports

VHDL generics
- VHDL generics

optimizing Verilog performance
- vlog

saving simulations
- WLF files (datasets) and virtuals
- log
- vsim
- Saving and viewing waveforms in batch mode

saving waveform as a Postscript file
- Printing and saving waveforms

setting default run length
- Default settings tab

setting iteration limit
- Default settings tab

setting time resolution
- Design selection tab

specifying design unit
- vsim

specifying the time unit for delays
- Simulation time units

speeding-up with Performance Analyzer
- Performance Analyzer

stepping through a simulation
- step

stopping simulation in batch mode
- when

Verilog
- Simulation

delay modes
- Delay modes

event order issues
- Event order issues

hazard detection
- Event order issues

optimizing performance
- Compiling for faster performance

resolution limit
- Simulation resolution limit

XL compatible simulator options
- Verilog-XL compatible simulator options

VHDL
- Simulating VHDL designs

invoking code coverage
- Invoking Code Coverage with Vsim

viewing results in List window
- List window

with the graphic interface
- Simulating with the graphic interface

with VITAL packages
- Compiling and Simulating with accelerated VITAL packages

Simulations

saving results
- WLF files (datasets) and virtuals

simulator resolution

returning as a real
- get_resolution()

when comparing datasets
- WLF files (datasets)

simulator time resolution (vsim -t)
- vsim

simulator version
- vsim
- vsim<info>

simultaneous events in Verilog

changing order
- vlog

sizetf callback function
- The sizetf callback function

sm_entity
- Creating foreign architectures with sm_entity

SmartModels

creating foreign architectures with sm_entity
- Creating foreign architectures with sm_entity

invoking SmartModel specific commands
- Command channel

linking to
- VHDL SmartModel interface

lmcwin commands
- SmartModel lmcwin commands

memory arrays
- Memory arrays

Verilog interface
- Verilog SmartModel interface

VHDL interface
- VHDL SmartModel interface

so, shared object file

loading PLI/VPI applications
- Compiling and linking PLI/VPI applications

Software updates
- Technical support and updates

software version
- Help menu

Sorting

sorting HDL items in VSIM windows
- Sorting HDL items

Source code

source code security
- Source code security and -nodebug

Source directory, setting from source window
- File menu

Source files

referencing with location maps
- Referencing source files with location maps

Source window
- Source window

spaces in pathnames
- File and directory pathnames

Specify path delays
- Verilog-XL compatible simulator options
- vsim

Speeding-up the simulation
- Performance Analyzer

splitio command
- splitio

Stability checking

disabling
- check stable off

enabling
- check stable on

Standards supported
- Standards supported

Startup

alternate to startup.do (vsim -do)
- vsim

environment variables access during
- Environment variables accessed during startup

files accessed during
- Files accessed during startup

macro in the modelsim.ini file
- [vsim] simulator control variables

startup macro in command-line mode
- Command-line mode

using a startup file
- Using a startup file

Startup .ini file variable
- [vsim] simulator control variables

Startup macros
- Using a startup file

Status bar

Main window
- The Main window status bar

status command
- status

std .ini file variable
- [Library] library path variables

std_developerskit .ini file variable
- [Library] library path variables

Std_logic

mapping to binary radix
- Searching for binary signal values in the GUI

std_logic_arith package
- Alternate IEEE libraries supplied

std_logic_signed package
- Alternate IEEE libraries supplied

std_logic_unsigned package
- Alternate IEEE libraries supplied

StdArithNoWarnings .ini file variable
- [vsim] simulator control variables

STDOUT environment variable
- Environment variables

step command
- step

Stimulus

applying to signals and nets
- Forcing signal and net values

stop command
- stop

Structure window
- Structure window

Support
- Technical support and updates

Symbolic link to design libraries (UNIX)
- Unix symbolic links

Synopsis Hardware Modeler
- VHDL Hardware Model interface

synopsys .ini file variable
- [Library] library path variables

system calls

VCD
- ModelSim VCD commands and VCD tasks

Verilog
- System Tasks

System commands
- System commands

System initialization
- System initialization

system tasks

VCD
- ModelSim VCD commands and VCD tasks

Verilog
- System Tasks

T

tab stops

in the Source window
- Setting tab stops in the Source window

tb command
- tb

Tcl
- Tcl and macros
- Description

command separator
- Command separator

command substitution
- Command substitution

command syntax
- Tcl command syntax

evaluation order
- Evaluation order

history shortcuts
- Command history shortcuts
- Command history shortcuts

Man Pages in Help menu
- Help menu

preference variables
- Preference variables located in Tcl files

relational expression evaluation
- Tcl relational expression evaluation

variable substitution
- Variable substitution

VSIM Tcl commands
- ModelSim Tcl commands

Technical support
- Technical support and updates

test region
- Compare by Region

test signals
- Introduction

Text and command syntax
- Text conventions

Text editing
- Mouse and keyboard shortcuts
- Mouse and keyboard shortcuts in Main and Source windows

TextIO package

alternative I/O files
- Using alternative input/output files

containing hexadecimal numbers
- Reading and writing hexadecimal numbers

dangling pointers
- Dangling pointers

ENDFILE function
- The ENDFILE function

ENDLINE function
- The ENDLINE function

file declaration
- Syntax for file declaration

implementation issues
- TextIO implementation issues

providing stimulus
- Providing stimulus

standard input
- Using STD_INPUT and STD_OUTPUT within ModelSim

standard output
- Using STD_INPUT and STD_OUTPUT within ModelSim

WRITE procedure
- TextIO implementation issues

WRITE_STRING procedure
- TextIO implementation issues

TF routines
- IEEE Std 1364 TF routines

TFMPC

disabling warning
- vsim

Time

simulation time units
- Simulation time units

time resolution as a simulator state variable
- Simulator state variables

Time resolution

in Verilog
- Simulation resolution limit

setting

with vsim command
- Selecting the time resolution
- vsim

setting in the GUI
- Design selection tab

time type

converting to real
- to_real()

Time-based breakpoints
- Setting signal breakpoints

timescale directive warning

disabling
- vsim

Timing

annotation
- Standard Delay Format (SDF) Timing Annotation

differences shown by comparison
- Wave window display

handling negative timing constraints
- Verilog-XL compatible system tasks

TMPDIR environment variable
- Environment variables

to_real VHDL function
- to_real()

to_time VHDL function
- to_time()

toggle add command
- toggle add

Toggle checking
- Toggle checking

toggle report command
- toggle report

toggle reset command
- toggle reset

Toggle statistics

enabling
- toggle add

reporting
- toggle report

resetting
- toggle reset

toggling Waveform popup on/off
- Waveform pane
- Setting Wave window display properties
- Wave window display

tolerance

leading edge
- Compare by Signal
- Compare by Region

trailing edge
- Compare by Signal
- Compare by Region

Toolbar

Main window
- The Main window toolbar

Wave window
-

Tracing HDL items with the Dataflow window
- Tracing HDL items with the Dataflow window

transcribe command
- transcribe

transcript command
- transcript

Transcript file

redirecting with -l
- vsim

saving
- Saving the Main window transcript file
- Creating a transcript file

TranscriptFile variable in .ini file
- [vsim] simulator control variables

Tree windows

VHDL and Verilog items in
- Tree window hierarchical view

viewing the design hierarchy
- Viewing the hierarchy

TreeUpdate command
- write format

Triggers, setting in the List window
- Trigger settings tab
- Setting up a List trigger with Expression Builder

TSCALE

disabling warning
- vsim

TSSI
- write tssi

in VCD files
- Supported TSSI states

tssi2mti command
- tssi2mti

type

converting real to time
- to_time()

converting time to real
- to_real()

U

-u
- Verilog-XL compatible compiler options

Unbound Component
- Setting default compile options

UnbufferedOutput .ini file variable
- [vsim] simulator control variables

up command
- up

UpCase .ini file variable
- [vlog] Verilog compiler control variables

Updates
- Technical support and updates

Use 1076-1993 language standard
- Setting default compile options

Use clause

specifying a library
- Predefined libraries

Use explicit declarations only
- Setting default compile options

User-defined bus
- Virtual Objects (User-defined buses, and more)
- Combining signals into a user-defined bus

UserTimeUnit .ini file variable
- [vsim] simulator control variables

util package
- Util package

V

-v
- Options supporting source libraries
- vlog

Values

describe HDL items
- describe

examine HDL item values
- examine

of HDL items
- Checking HDL item values and descriptions

replacing signal values with strings
- virtual type

Variable settings report
- ModelSim variables

Variables

environment variables
- Environment variables

LM_LICENSE_FILE
- Environment variables

loading order at ModelSim startup
- System initialization

personal preferences
- Personal preferences

precedence between .ini and .tcl
- Variable precedence

reading from the .ini file
- Reading variable values from the INI file

setting environment variables
- Environment variables

simulator state variables

current settings report
- Variable settings report

iteration number
- Simulator state variables

name of entity or module as a variable
- Simulator state variables

resolution
- Simulator state variables

simulation time
- Simulator state variables

Variables window
- Variables window

Variables, HDL

changing value of on command line
- change

changing value of with the GUI
- Variables window

describing
- describe

examining values
- examine

Variables, Tcl
- ModelSim variables

vcd add command
- vcd add

vcd checkpoint command
- vcd checkpoint

vcd comment command
- vcd comment

vcd dumpports command
- vcd dumpports

vcd dumpportsall command
- vcd dumpportsall

vcd dumpportsflush command
- vcd dumpportsflush

vcd dumpportslimit command
- vcd dumpportslimit

vcd dumpportsoff command
- vcd dumpportsoff

vcd dumpportson command
- vcd dumpportson

vcd file command
- vcd file

VCD files
- Value Change Dump (VCD) Files

adding internal signals
- vcd add

adding items to the file
- vcd add

capturing port driver data
- Capturing port driver data
- vcd dumpports

converting to WLF files
- vcd2wlf

creating
- Creating a VCD file
- vcd add

dumping variable values
- vcd checkpoint

dumpports tasks
- ModelSim VCD commands and VCD tasks

flushing the buffer contents
- vcd flush

from VHDL source to VCD output
- A VCD file from source to output

inserting comments
- vcd comment

specifying maximum file size
- vcd limit

specifying name of
- vcd files

specifying the file name
- vcd file

state mapping
- vcd file
- vcd files

supported TSSI states
- Supported TSSI states

turn off VCD dumping
- vcd off

turn on VCD dumping
- vcd on

VCD system tasks
- ModelSim VCD commands and VCD tasks

viewing files from another tool
- vcd2wlf

vcd files command
- vcd files

vcd flush command
- vcd flush

vcd limit command
- vcd limit

vcd off command
- vcd off

vcd on command
- vcd on

vcd2wlf command
- vcd2wlf

vcom command
- vcom

vdel command
- vdel

vdir command
- vdir

Verilog

ACC routines
- IEEE Std 1364 ACC routines

capturing port driver data with -dumpports
- Capturing port driver data
- vcd file

cell libraries
- Cell Libraries

compiler directives
- Compiler Directives

compiling and linking PLI applications
- Compiling and linking PLI/VPI applications

compiling design units
- Compilation

compiling with XL 'uselib compiler directive
- Verilog-XL `uselib compiler directive

component declaration
- vgencomp component declaration

creating a design library
- Compilation

instantiation criteria in mixed-language design
- VHDL instantiation of Verilog design units

instantiation of VHDL design units
- Verilog instantiation of VHDL design units

library usage
- Library usage

mapping states in mixed designs
- Verilog states

mixed designs with VHDL
- Mixed VHDL and Verilog Designs

parameters
- Verilog parameters

SDF annotation
- Verilog SDF

sdf_annotate system task
- Verilog SDF

simulating
- Simulation

delay modes
- Delay modes

event order issues
- Event order issues

XL compatible options
- Verilog-XL compatible simulator options

simulation hazard detection
- Event order issues

simulation resolution limit
- Simulation resolution limit

SmartModel interface
- Verilog SmartModel interface

source code viewing
- Source window

standards
- Standards supported

system tasks
- System Tasks

TF routines
- IEEE Std 1364 TF routines

XL compatible compiler options
- Verilog-XL compatible compiler options

XL compatible routines
- Verilog-XL compatible routines

XL compatible system tasks
- Verilog-XL compatible system tasks

verilog .ini file variable
- [Library] library path variables

Verilog PLI/VPI
- Verilog PLI/VPI
- PLI/VPI tracing

64-bit support in the PLI
- 64-bit support in the PLI

compiling and linking PLI/VPI applications
- Compiling and linking PLI/VPI applications

debugging PLI/VPI code
- PLI/VPI tracing

PLI callback reason argument
- The PLI callback reason argument

PLI support for VHDL objects
- Support for VHDL objects

registering PLI applications
- Registering PLI applications

registering VPI applications
- Registering VPI applications

specifying the PLI/VPI file to load
- Specifying the PLI/VPI file to load

Verilog Procedural Interface
- Verilog PLI/VPI

Verilog XL

differences in event order
- Event order issues

Veriuser .ini file variable
- Registering PLI applications
- [vsim] simulator control variables

version

obtaining via Help menu
- Help menu

obtaining with vsim command
- vsim

obtaining with vsim<info> commands
- vsim<info>

vgencomp command
- vgencomp

VHDL

compiling design units
- Compiling VHDL designs

creating a design library
- Compiling VHDL designs

delay file opening
- Opening VHDL files

dependency checking
- Dependency checking

field naming syntax
- Naming fields in VHDL signals

file opening delay
- Opening VHDL files

foreign language interface
- Foreign language interface

Hardware Model interface
- VHDL Hardware Model interface

instantiation from Verilog
- Verilog instantiation of VHDL design units

instantiation of Verilog
- Mapping data types

library clause
- Specifying the resource libraries

mixed designs with Verilog
- Mixed VHDL and Verilog Designs

object support in PLI
- Support for VHDL objects

simulating
- Simulating VHDL designs

SmartModel interface
- VHDL SmartModel interface

source code viewing
- Source window

standards
- Standards supported

VITAL package
- Alternate IEEE libraries supplied

VHDL utilities
- Util package
- init_signal_spy()

get_resolution()
- get_resolution()

to_real()
- to_real()

to_time()
- to_time()

VHDL93 .ini file variable
- [vcom] VHDL compiler control variables

view command
- view

view_profile command
- Viewing Performance Analyzer Results

view_profile_ranked command
- Viewing Performance Analyzer Results

Viewing

design hierarchy
- Tree window hierarchical view

library contents
- Managing library contents

waveforms
- vsim

Viewing and saving waveforms
- WLF files (datasets) and virtuals

virtual count commands
- virtual count

virtual define command
- virtual define

virtual delete command
- virtual delete

virtual describe command
- virtual describe

virtual expand commands
- virtual expand

virtual function command
- virtual function

virtual hide command
- Virtual signals
- virtual hide

virtual log command
- virtual log

virtual nohide command
- virtual nohide

virtual nolog command
- virtual nolog

Virtual objects
- Virtual Objects (User-defined buses, and more)

virtual functions
- Virtual functions

virtual regions
- Virtual regions

virtual signals
- Virtual signals

virtual types
- Virtual types

virtual region command
- Virtual regions
- virtual region

Virtual regions

reconstruct the RTL Hierarchy in gate level design
- Virtual regions

virtual save command
- Virtual signals
- virtual save

virtual show command
- virtual show

virtual signal command
- Virtual signals
- virtual signal

Virtual signals

reconstruct RTL-level design busses
- Virtual signals

reconstruct the original RTL hierarchy
- Virtual signals

virtual hide command
- Virtual signals

virtual type command
- virtual type

VITAL

compiling and simulating with accelerated VITAL packages
- Compiling and Simulating with accelerated VITAL packages

compliance warnings
- VITAL compliance warnings

obtaining the specification and source code
- Obtaining the VITAL specification and source code

VITAL 2000 library
- VITAL 2000 library

VITAL packages
- ModelSim VITAL compliance

vlib command
- vlib

vlog command
- vlog

vmake command
- vmake

vmap command
- vmap

VPI

registering applications
- Registering VPI applications

VPI/PLI
- Verilog PLI/VPI

compiling and linking applications
- Compiling and linking PLI/VPI applications

VSIM build date and version
- vsim<info>

vsim command
- vsim

W

Warnings

disabling individual compiler warnings
- vcom

disabling specific warning messages
- vlog
- vsim

turning off warnings from arithmetic packages
- Turning off warnings from arithmetic packages

wave

adding
- add wave

Wave format file
- Adding HDL items in the Wave window

Wave log format (WLF) file
- WLF files (datasets) and virtuals
- vsim

of binary signal values
- log

Wave window
- Wave window

compare waveforms
- Wave window display

toggling Waveform popup on/off
- Waveform pane
- Setting Wave window display properties
- Wave window display

values column
- Wave window display

WaveActivateNextPane command
- write format

Waveform Comparison
- Waveform Comparison
- compare add

add clock
- Compare by Signal

add region
- Compare by Region

adding signals
- Adding Signals, Regions and/or Clocks

clear differences
- Compare menu

clocked comparison
- Clocked Compare
- Compare by Signal
- Compare by Region

compare by region
- Compare by Region

compare by signal
- Compare by Signal

compare commands
- Waveform Comparison commands

compare menu
- Compare menu

compare options
- Setting Compare Options

compare tab
- Test Dataset

comparison method
- Setting Compare Options

comparison method tab
- Compare by Region

comparison modes
- Two Modes of Comparison

comparison wizard
- Compare menu

continuous comparison
- Continuous Compare
- Compare by Signal
- Compare by Region

dataset
- Introduction

difference markers
- Wave window display

end
- Compare menu

features
- Introduction

flattened designs
- Comparing Hierarchical and Flattened Designs

graphic interface
- Graphic Interface to Waveform Comparison

hierarchical designs
- Comparing Hierarchical and Flattened Designs

icons
- Compare icons

introduction
- Introduction

leading edge tolerance
- Compare by Signal
- Compare by Region

limit count
- Setting Compare Options

List window display
- List window display

modify clock
- Compare by Signal

pathnames
- Wave window display

preference variables
- Waveform Comparison preference variables

printing differences
- Printing compare differences

reference dataset
- Reference Dataset

reference region
- Compare by Region

reference signals
- Introduction

reload
- Compare menu

rules
- Compare menu

run

run comparison
- Compare menu

save differences
- Compare menu

show differences
- Compare menu

signal options
- Compare by Signal

specify when expression
- Compare by Signal
- Compare by Region
- Compare by Region

specifying a dataset
- Test Dataset

start
- Compare menu

Tcl preference variables
- Waveform Comparison preference variables

test dataset
- Test Dataset

test region
- Compare by Region

test signals
- Introduction

timing differences
- Wave window display

tolerances
- Continuous Compare

trailing edge tolerance
- Compare by Signal
- Compare by Region

values column
- Wave window display

Verilog matching
- Setting Compare Options

VHDL matching
- Setting Compare Options

Wave window display
- Wave window display

when statement
- Compare by Region

write report
- Compare menu

Waveform logfile

log command
- log

overview
- WLF files (datasets) and virtuals

Waveform popup
- Waveform pane
- Setting Wave window display properties
- Wave window display

Waveforms
- WLF files (datasets) and virtuals

halting drawing
- .wave.tree interrupt

saving and viewing
- WLF files (datasets)
- log

saving and viewing in batch mode
- Saving and viewing waveforms in batch mode

viewing
- Wave window

WaveRestoreCursors command
- write format

WaveRestoreZoom command
- write format

WaveSignalNameWidth .ini file variable
- [vsim] simulator control variables

Welcome dialog

turning on/off
- Personal preferences

when command
- when

when statement

setting signal breakpoints
- Setting signal breakpoints

specifying for waveform comparison
- Compare by Region

time-based breakpoints
- when

where command
- where

Wildcard characters

for pattern matching in simulator commands
- Wildcard characters

Windows

finding HDL item names
- Finding names, searching for values, and locating cursors

opening from command line
- view

opening multiple copies
- Multiple window copies

opening with the GUI
- View menu

searching for HDL item values
- Finding names, searching for values, and locating cursors

adding buttons
- The Button Adder

coverage_source
- The coverage_source window

coverage_summary
- The coverage_summary window

Dataflow window
- Dataflow window

tracing signals and nets
- Tracing HDL items with the Dataflow window

List window
- List window

adding HDL items
- Adding HDL items to the List window

adding signals with a WLF file
- Adding HDL items to the Wave and List windows or a WLF file

examining simulation results
- Examining simulation results with the List window

formatting HDL items
- Editing and formatting HDL items in the List window

locating time markers
- Finding names, searching for values, and locating cursors

output file
- write list

saving the format of
- write format

saving to a file
- Saving List window data to a file

setting display properties
- Setting List window display properties

setting triggers
- Trigger settings tab
- Setting up a List trigger with Expression Builder

Main window
- Main window

adding user-defined buttons
- add button

status bar
- The Main window status bar

text editing
- Mouse and keyboard shortcuts
- Mouse and keyboard shortcuts in Main and Source windows

time and delta display
- The Main window status bar

toolbar
- The Main window toolbar

Process window
- Process window

displaying active processes
- Process window

specifying next process to be executed
- Process window

viewing processing in the region
- Process window

saving position and size
- Saving window layout

Signals window
- Signals window

VHDL and Verilog items viewed in
- Signals window

Source window
- Source window

setting tab stops
- Setting tab stops in the Source window

text editing
- Mouse and keyboard shortcuts
- Mouse and keyboard shortcuts in Main and Source windows

viewing HDL source code
- Source window

Structure window
- Structure window

HDL items viewed in
- Structure window

instance names
- Instance name components in the Structure window

selecting items to view in Signals window
- Signals window

VHDL and Verilog items viewed in
- Structure window

viewing design hierarchy
- Structure window

Variables window
- Variables window

displaying values
- Variables window

VHDL and Verilog items viewed in
- Variables window

Wave window
- Wave window

adding HDL items
- Adding HDL items in the Wave window

adding signals with a WLF file
- Adding HDL items to the Wave and List windows or a WLF file

changing display range (zoom)
- Zooming - changing the waveform display range

changing path elements
- configure
- [vsim] simulator control variables

cursor measurements
- Making cursor measurements

locating time cursors
- Finding names, searching for values, and locating cursors

saving format file
- Adding HDL items in the Wave window

searching for HDL item values
- Searching for item values in the Wave window

setting display properties
- Setting Wave window display properties

using time cursors
- Using time cursors in the Wave window

zoom options
- Zooming - changing the waveform display range

zooming
- Zooming - changing the waveform display range

WLF files

adding items to
- Adding HDL items to the Wave and List windows or a WLF file

comparing
- Introduction

creating from VCD
- vcd2wlf

limiting size
- vsim

log command
- log

overview
- WLF files (datasets)

saving
- Saving a simulation to a WLF file

specifying name
- vsim

using in batch mode
- Saving and viewing waveforms in batch mode

wlf2log command
- wlf2log

Work library
- Design library types

workspace
- Workspace

write

waveform comparison report
- Compare menu

write format command
- write format

write list command
- write list

write preferences command
- write preferences

write report command
- write report

write transcript command
- write transcript

write tssi command
- write tssi

write wave command
- write wave

X

X propagation

preventing
- vsim

Y

-y
- Options supporting source libraries
- vlog

Z

Zero-delay loop, detecting infinite
- Detecting infinite zero-delay loops

Zero-delay oscillation
- Detecting infinite zero-delay loops

Zoom

from Wave toolbar buttons
- Zooming - changing the waveform display range

from Zoom menu
- Zooming - changing the waveform display range

options
- Zooming - changing the waveform display range

saving range with bookmarks
- Saving zoom range and scroll position with bookmarks

with the mouse
- Zooming - changing the waveform display range