Turning off assertion messages

You can turn off assertion messages from your VHDL code by setting a switch in the modelsim.ini file. This option was added because some utility packages print a huge number of warnings.

[vsim]
IgnoreNote = 1
IgnoreWarning = 1
IgnoreError = 1
IgnoreFailure = 1 

Messages may also be turned off with Tcl variables; see "Preference variables located in Tcl files" .

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