Table of Contents Previous page Next page Index

ModelSim Documentation Bookcase

Model Technology Inc.


Signal attributes

<name>'event
<name>'rising
<name>'falling
<name>'delayed()

The 'delayed attribute lets you assign a delay to a VHDL signal. To assign a delay to a signal in Verilog, use "#" notation in a subexpression (e.g., #-10 /top/signalA). See "Examples" below for further details.


Model Technology Inc.
Model Technology Incorporated
Voice: (503) 641-1340
Fax: (503)526-5410
www.model.com
sales@model.com
Table of Contents Previous page Next page Index

ModelSim Documentation Bookcase