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Array variables

Variable
Type
Name of a signal
-- VHDL signals of type bit_vector or std_logic_vector
-- VLOG register
-- VLOG net array
A subrange or index may be specified in either VHDL or VLOG syntax. Examples: mysignal(1 to 5), mysignal[1:5], mysignal (4), mysignal [4]


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ModelSim Documentation Bookcase