Overviews

Commands

See Also

To specify EDA tool settings:

1. If you have not already done so, create a new project or open an existing project.

2. Choose Settings (Assignments menu) Shortcut.

3. In the Categories list, select EDA Tool Settings.

4. Specify the design entry or synthesis tool:

   1. In the EDA tools list, select Design entry/synthesis.

   2. In the Tool name list, select the name of design entry or synthesis tool, or select Custom. More Details

   3. Click Settings.

   4. In the EDA Tool Input Settings dialog box, specify EDA tool input settings.

   5. If you select a specific design entry or synthesis tool and want to have that tool generate a compilable netlist automatically from the source files when they change, turn on Generate a compilable netlist automatically from the source files when they change.  More Details

5. Specify the simulation tool:

1. In the EDA tools list, select Simulation.

2. Under Tool settings, in the Tool name list, select the name of the simulation tool you want to use.  More Details

3. If necessary, specify VHDL output settings or specify Verilog HDL output settings for the selected simulation tool.

4. If you selected a specific VHDL or Verilog HDL simulation tool and want to run the tool automatically after compilation, turn on Run this tool automatically after compilation in the EDA Tool Settings page of the Settings dialog box (Assignments menu).  More Details

5. If you selected the ModelSim^® software in the Tool name list, and you turned on Run this tool automatically after compilation, you can specify advanced options for simulation.

6. Specify the timing analysis tool:

1. In the EDA tools list, select Timing analysis.  More Details

2. Under Tool settings, in the Tool name list, select the name of the timing analysis tool.

3. If necessary, specify VHDL output settings or specify Verilog HDL output settings for the selected timing analysis tool.

4. If you selected a specific VHDL or Verilog HDL timing analysis tool and want to run the tool automatically after compilation, turn on Run this tool automatically after compilation.

7. Specify the board-level verification tool for generating PartMiner edaXML-Format Files (.xml) and for generating IBIS Output Files (.ibs):

   IBIS model generation is fully supported for all devices supported by the Quartus® II software, except Cyclone™ and Stratix™ GX devices. For additional IBIS model device support and support files, refer to the "IBIS models" section of the Device Support section on the Altera® web site.

   1. In the EDA tools list, select Board-level.

   2. Under Tool settings, in the Tool name list, select the name of the board-level verification tool.  More Details

   3. If necessary, specify IBIS output settings.

8. Specify the formal verification tool:

   1. Under Tool settings, in the EDA tools list, select Formal verification.

   2. Under Tool settings, in the Tool name list, select the name of the formal verification tool.

9. Specify the resynthesis tool:

   1. In the EDA tools list, select Resynthesis.

   2. Under Tool settings, in the Tool name list, select the resynthesis tool.

   3. If necessary, specify resynthesis output settings.

   4. Turn on Run this tool automatically after compilation.

10. Click OK.

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