See Also

In the EDA Tool Settings page of the Settings dialog box (Assignments menu), you can select Simulation or Timing analysis in the EDA tools list, and select a Simulation tool or Timing analysis tool in the Tool name list, or select Custom VHDL, Custom Verilog HDL, or <none>.

If you are using the OEM version of the ModelSim^® software, specify ModelSim OEM (VHDL output from Quartus^® II) or ModelSim OEM (Verilog output from Quartus II) as the simulation tool. If you are using the full version of the ModelSim software, specify ModelSim (VHDL output from Quartus II) or ModelSim (Verilog output from Quartus II) as the simulation tool.

If you select a specific EDA tool, the Compiler selects the default Verilog HDL output settings or VHDL output settings for that tool.

If you have previously defined customized settings, you can select Custom VHDL or Custom Verilog HDL to use the customized settings.

If you specify VHDL output settings for a simulation or timing analysis tool, a VHDL Output File (.vho) and a Standard Delay Format Output File (.sdo) are created and placed in an tool-specific directory after you compile the design.

If you specify Verilog output settings for a simulation or timing analysis tool, a Verilog Output File (.vo) and an SDF Output File are created and placed in a tool-specific directory after you compile the design.

You can select Stamp (board model) in the Tool name after selecting Board-level in the EDA Tools list to perform timing verification on a board-level design and create the Stamp model files.

The tool specific directory created by the Quartus II software during compilation is located in a simulation or timing directory in the current project directory. This directory uses the name of the specified EDA simulation or timing analysis tool or custom if you specify Custom VHDL or Custom Verilog HDL.

If you use the default <none> selection, no settings will be defined, and no output files are generated.

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