EDA Interfaces

Specifying Verilog HDL Output Settings



To specify options for generating Verilog Output Files (.vo) and Standard Delay Format Output Files (.sdo) for use with other EDA tools:

  1. If you have not already done so, create a new project or open an existing project.

  2. Choose Settings (Assignments menu) Shortcut.

  3. In the Categories list, select EDA Tool Settings.

  4. In the EDA tools list, select Simulation or Timing analysis.

  5. In the Tool name list, select the name of a Verilog HDL simulation or timing analysis tool, or select Custom Verilog HDLMore Details

  6. Click Settings.

  7. In the Verilog HDL Output Settings dialog box, make sure you selected the correct Simulation tool or Timing analysis tool.

  8. In the Time scale list, select a time scale.

  9. If you want to map illegal Verilog HDL characters, turn on Map illegal Verilog HDL characters.

  10. If you want to truncate hierarchical node names to 80 characters or less, turn on Truncate long hierarchy paths.

  11. If you want to flatten all buses when creating the Verilog Output File, turn on Flatten buses into individual nodes.

  12. If you are targeting an ARM®-based Excalibur device and you want to perform a full stripe model simulation of the design, turn on Output Excalibur stripe as a single module.

  13. If you want to perform power estimation using the Model Technology ModelSim® software, turn on Generate Power Input File.

  14. If you want to add the devpor, devclrn, and devoe signals as input ports in the top-level design hierarchy in the Verilog Output File, turn on Bring out device-wide set/reset signals as ports.

  15. If you want to maintain the original design hierarchy in the Verilog Output File, turn on Maintain hierarchy.

  16. If you will be performing a timing simulation with the Verilog Output File, turn on Generate SDF Output File. If you will be performing a functional simulation, make sure Generate SDF Output File is turned off.

  17. If you want to restore the default Verilog HDL output settings for the simulation or timing analysis tool, click Reset.

  18. Click OK. More Details

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