See Also

The Quartus^® II software can interface with almost any industry-standard EDA tool that generates an EDIF 2 0 0 netlist file, a VHDL 1987 netlist file, VHDL 1993 netlist file, or a Verilog HDL netlist file. You can create a design with a standard EDA tool or with the Quartus II Text Editor, compile it with the Quartus II Compiler, and perform timing analysis with the Quartus II Timing Analyzer or a standard timing analysis tool. After compilation, you can simulate the design with the Quartus II Simulator, or with a standard simulator. You can then program the device with Altera^® programming software and hardware.

You can create and then compile Quartus II–compatible designs in several ways:

• Generate an EDIF netlist file from one of the following types of designs:

  - A schematic design created with an industry-standard EDA tool.

  - A Verilog HDL design created with a standard text editor and processed with a synthesis tool.

  - A VHDL design created with a standard text editor and processed with a synthesis tool.

  The Quartus II software can read both .edf and .edif extensions. You must change the EDIF netlist file name extension to .edf or .edif so that the Quartus II software can read the file as an EDIF Input File (.edf). The Quartus II software reads EDIF Input Files with the help of Library Mapping files (.lmf) that map logic functions from other EDA tools to Quartus II logic functions.

• Create a Text Design File (.tdf) in Altera Hardware Description Language (AHDL) with the Quartus II Text Editor or any standard text editor.
• Create a VHDL Design File (.vhd) with the Quartus II Text Editor, any standard text editor, or an industry-standard EDA tool.
• Create a Verilog Design File (.v) with the Quartus II Text Editor, any standard text editor, or an industry-standard EDA tool.
• Create a Verilog Quartus^® Mapping File (.vqm) with the Synplicity Synplify software.

Any Quartus II project can include one or more EDIF Input Files, VHDL Design Files, Verilog Design Files, VQM Files, Block Design Files (.bdf), and/or TDFs.

The Compiler can generate one or more output files for use with other industry-standard design verification tools:

• The Compiler generates a Verilog Output File (.vo) that contains postrouting and postpartitioning netlist information for simulation or timing analysis with a standard Verilog HDL simulator.

• The Compiler generates a VHDL Output File (.vho) that contains postrouting and postpartitioning netlist information for simulation or timing analysis with a standard VHDL simulator.

• The Compiler generates a Standard Delay Format Output File (.sdo) that contains timing delay information for use with VITAL-compatible libraries or Verilog HDL libraries.

• The Compiler generates STAMP model files for performing board-level timing analysis.

• The Compiler generates an IBIS Output File (.ibs) for performing board-level signal integrity verification.

• The Compiler generates a PartMiner edaXML-Format File (.xml) for symbol generation with other EDA tools.

The Compiler also generates a file for timing simulation or timing analysis with the Quartus II Simulator or Timing Analyzer, respectively. In addition, it generates one or more programming files that you can use to program devices with the Quartus II Programmer and other Altera programming hardware.

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