Procedures

Commands

See Also

The Quartus^® II software interfaces with many industry-standard EDA tools.

The Quartus II software can read EDIF Input Files (.edf), Verilog Quartus^® Mapping Files (.vqm), VHDL Design Files (.vhd), and Verilog Design Files (.v) created by most popular design entry/synthesis tools, including Synopsys^® Design Compiler, Synopsys FPGA Express, Mentor Graphics^® LeonardoSpectrum^™, Synplicity Synplify and Synplify Pro, and Innoveda ViewDraw software.

The Quartus II software can generate VHDL Output Files (.vho), Verilog Output Files (.vo), Standard Delay Format Output Files (.sdo), and Stamp model files for use with most industry-standard EDA simulation and timing analysis tools, including Cadence Verilog-XL, NC-Verilog, and NC-VHDL software; Mentor Graphics Tau software; Model Technology^™ ModelSim^® software; Innoveda BLAST and SpeedWave software; and Synopsys VSS, VCS, PrimeTime, and Scirocco software.

In the EDA Tool Settings page of the Settings dialog box (Assignments menu), you can specify options for the EDA tools you are using in the project. You can direct the Quartus II software to run a design entry or synthesis tool as a background process to regenerate source netlists when the original source files change. You can also direct the Quartus II software to run a simulation or timing analysis tool automatically after compilation. You can specify additional options for input and output files in other dialog boxes that are available from the EDA Tool Input Settings dialog box:

• In the EDA Tool Input Settings dialog box, you can specify EDA tool input settings, including specifying Library Mapping Files (.lmf) for processing EDIF Input Files, VHDL Design Files, Verilog Design Files, Verilog Quartus Mapping Files, and AHDL Text Design Files that were generated by other design entry or synthesis tools.
• In the Verilog HDL Output Settings dialog box, you can specify Verilog HDL output settings for generating Verilog Output Files and SDF Output Files for use with other simulation or timing analysis tools.
• In the VHDL Output Settings dialog box, you can specify VHDL output settings for generating VHDL Output Files and SDF Output Files for use with other simulation or timing analysis tools.
• In the Advanced Verilog Simulation Options and Advanced VHDL Simulation Options dialog boxes, you can specify advanced options for simulating Verilog Output Files and VHDL Output Files with the Model Technology ModelSim software.

• In the IBIS Output Settings dialog box, you can specify options for generating IBIS Output Files (.ibs) for board-level signal integrity verification with other EDA tools.

• In the Resynthesis Tool Settings dialog box, you can specify options for performing resynthesis with other EDA tools.

You can generate Verilog Output Files, VHDL Output Files, SDF Output Files, Stamp model files, PartMiner XML-Format Files (.xml), and IBIS Output Files (.ibs) after compilation of the design with the EDA Tool Post-Compilation Commands > Write Output Netlists command (Processing menu).

You can also use the EDA Tool Post-Compilation Commands > Generate Test Bench Template (Processing menu) and Run Simulation Tool (Tools menu) commands to generate Verilog Test Bench Files (.vt) and VHDL Test Bench Files (.vht), and to run a simulation tool without recompiling the design.

More information is available on other EDA design entry/synthesis and simulation tools on the Altera® web site.

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