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To specify options for simulating Verilog Output Files (.vo) and VHDL Output Files (.vho) automatically after compilation in the Quartus^® II software using other EDA tools:

1. If you have not already done so, create a new project or open an existing project.

2. Choose Settings (Assignments menu) Shortcut.

3. In the Categories list, select EDA Tool Settings.

4. In the Simulation tool list, select ModelSim^® (VHDL output from Quartus II), ModelSim (Verilog output from Quartus II), ModelSim OEM (Verilog output from Quartus II), or ModelSim OEM (VHDL output from Quartus II).

5. Select Run this tool automatically after compilation.

6. Click Advanced.

7. To select options for simulating in test bench mode:

   1. Turn on Test Bench mode.

   2. In the Test Bench file box, select or type the name of the test bench file you want to simulate.

   3. In the Test Bench entity name box, type the name of the top-level design entity in the test bench file.

   4. If you have a VHDL design, in the Test Bench design instance name box, type the name of the design instance in the test bench file.

   5. In the Run for box, type the simulation time and select the time units.

   6. Click OK.

8. Select command/macro mode:

   1. Turn on Command/macro mode.

   2. Type or browse to the location of the Model Technology^™ ModelSim Macro File (.do), TCL Script File (.tcl), or batch file that contains the simulation commands.

   The file that is specified under Command/macro mode is executed from within the <project directory>\simulation\modelsim directory.

   3. Click OK.

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