See Also

Directs the selected simulation, timing analysis, or resynthesis EDA tool to start automatically after the Quartus^® II software compiles the design. You must also turn this option on if you want to specify advanced simulation options.

The simulation or timing analysis tool processes the VHDL Output Files (.vho), Verilog Output Files (.vo), and Standard Delay Format Output Files (.sdo) that are generated during compilation.

The resynthesis tool generates the appropriate output files and launches the Quartus II software to recompile the project after performing resynthesis.