A Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) standard netlist file (with the extension .vho) that is generated by the Quartus^® II Compiler.

The VHDL Output File is a VHDL version 1987 standard netlist file that can be imported into an industry-standard VHDL simulation or timing analysis tool. A VHDL Output File cannot be compiled with the Quartus II Compiler.

You can specify that the Compiler generates a VHDL Output File after successful compilation by selecting the name of the specific VHDL simulation or timing analysis tool or by selecting Custom VHDL from the Tool name list in the EDA Tool Settings page of the Settings dialog box (Assignments menu). You can then specify options for the VHDL Output File in the VHDL Output Settings dialog box, which is available from the EDA Tool Settings page of the Settings dialog box (Assignments menu).

You can also generate a VHDL Output File by using the EDA Tool Post-Compilation Commands > Write Output Netlists command (Processing menu). You can use this command if you have already compiled the design and want to change the EDA tool settings and generate a VHDL Output File for another EDA tool.

The Compiler places the generated VHDL Output File into a tool-specific directory within the current project directory. For EDA simulation tools, the VHDL Output File is placed in the /<project directory>/simulation/<EDA simulation tool> directory. For EDA timing analysis tools, the VHDL Output File is placed in the /<project directory>/timing/<EDA timing analysis tool> directory. If you select Custom VHDL for simulation or timing analysis, the VHDL Output File is placed in the /<project directory>/simulation/custom directory or /<project directory>/timing/custom directory, respectively.

The file name of the VHDL Output File is the top-level design entity name with a .vho extension. The file name of the Standard Delay Format Output File (.sdo) is the top-level design entity name with a "_vhd" appended to the project name and an .sdo extension (that is, <top-level design name>_vho.sdo). The VHDL Output File contains properties of all entities within the top-level project.

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